diff options
| author | Joseph Lo <josephl@nvidia.com> | 2012-10-31 17:41:18 +0800 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-11-15 15:09:21 -0700 |
| commit | fe508d776908b8512c6d936eb29e40bef1f4b8fc (patch) | |
| tree | 5754a56879d50a4f2b5eef6d0558a71938bab424 /arch/arm/mach-tegra | |
| parent | d457ef358f3c7179c428becda45b1dfd2b8cf98a (diff) | |
ARM: tegra30: common: enable csite clock
Enable csite (debug and trace controller) clock at init to prevent it
be disabled. And this also the necessary clock for CPU be brought up or
resumed from a power-gating low power state.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 3e03e5f15c1..203a8b94863 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -108,6 +108,7 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { { "sclk", "pll_p_out4", 102000000, true }, { "hclk", "sclk", 102000000, true }, { "pclk", "hclk", 51000000, true }, + { "csite", NULL, 0, true }, { NULL, NULL, 0, 0}, }; #endif |