ux500: PRCMU: Fix redefinitions to support all Ux500 platforms in same kernel

Minimal changes has been made to ease future merge from Android branch,
a better solution is to set up a PRCMU operations structure.

Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org>

7 files changed, 166 insertions, 32 deletions

diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 4fbb7e4d6dc..db2fbd8463f 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -20,11 +20,14 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_DEFAULT_DEADLINE=y
 CONFIG_ARCH_U8500=y
+CONFIG_UX500_SOC_DB5500=y
 CONFIG_UX500_SOC_DB8500=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
+CONFIG_MACH_U5500=y
 CONFIG_UX500_PRCMU_TIMER=y
 CONFIG_DB8500_MLOADER=y
+CONFIG_U5500_MLOADER=y
 CONFIG_UX500_DEBUG_HWREG=y
 CONFIG_MCDE_DISPLAY_PRIMARY_32BPP=y
 CONFIG_DISPLAY_GENERIC_DSI_PRIMARY_VSYNC=y
@@ -121,6 +124,7 @@ CONFIG_SMSC911X=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_DB5500=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_NOMADIK_SKE=y
 CONFIG_KEYBOARD_STMPE=y
@@ -218,9 +222,10 @@ CONFIG_RTC_DRV_AB8500=y
 CONFIG_DMADEVICES=y
 CONFIG_STE_DMA40=y
 CONFIG_STAGING=y
+CONFIG_U5500_MMIO=y
 CONFIG_U8500_MMIO=y
-CONFIG_U8500_CM=y
 CONFIG_U8500_FLASH=y
+CONFIG_U8500_CM=y
 # CONFIG_STAGING_EXCLUDE_BUILD is not set
 CONFIG_AUTOFS_FS=m
 CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index 0f0062c4b97..eb4b25b7623 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -223,7 +223,7 @@ void __init u5500_init_devices(void)
 {
 #ifdef CONFIG_STM_TRACE
 	/* Early init for STM tracing */
-	platform_device_register(&ux500_stm_device);
+	/* platform_device_register(&u5500_stm_device); */
 #endif
 	db5500_add_gpios();
 	db5500_dma_init();
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-db5500.h b/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
index 0d26f72230e..2a43ea86516 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
@@ -11,21 +11,23 @@
 #ifdef CONFIG_UX500_SOC_DB5500
 
 void db5500_prcmu_early_init(void);
-
 int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
 int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
-
 int db5500_prcmu_request_clock(u8 clock, bool enable);
-
+void db5500_prcmu_enable_wakeups(u32 wakeups);
+int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state);
+int db5500_prcmu_set_display_clocks(void);
+int db5500_prcmu_disable_dsipll(void);
+int db5500_prcmu_enable_dsipll(void);
 int prcmu_resetout(u8 resoutn, u8 state);
 
-static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
 	bool keep_ap_pll)
 {
 	return 0;
 }
 
-static inline void prcmu_system_reset(u16 reset_code) {}
+static inline void db5500_prcmu_system_reset(u16 reset_code) {}
 
 #else /* !CONFIG_UX500_SOC_DB5500 */
 
@@ -43,11 +45,33 @@ static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
 	return -ENOSYS;
 }
 
+static inline int db5500_prcmu_set_display_clocks(void)
+{
+	return 0;
+}
+
+static inline int db5500_prcmu_disable_dsipll(void)
+{
+	return 0;
+}
+
+static inline int db5500_prcmu_enable_dsipll(void)
+{
+	return 0;
+}
+
+static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {}
+
 static inline int prcmu_resetout(u8 resoutn, u8 state)
 {
 	return 0;
 }
 
+static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
+{
+	return 0;
+}
+
 #endif /* CONFIG_UX500_SOC_DB5500 */
 
 static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events)
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-db8500.h b/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
index f5efd0d369c..7b620ddc4e9 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
@@ -209,6 +209,16 @@ int prcmu_stop_temp_sense(void);
 void prcmu_enable_spi2(void);
 void prcmu_disable_spi2(void);
 
+void db8500_prcmu_system_reset(u16 reset_code);
+int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+		bool keep_ap_pll);
+void db8500_prcmu_enable_wakeups(u32 wakeups);
+int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
+int db8500_prcmu_request_clock(u8 clock, bool enable);
+int db8500_prcmu_set_display_clocks(void);
+int db8500_prcmu_disable_dsipll(void);
+int db8500_prcmu_enable_dsipll(void);
+
 #else /* !CONFIG_UX500_SOC_DB8500 */
 
 static inline bool prcmu_is_u8400(void)
@@ -303,6 +313,39 @@ static inline int prcmu_disable_spi2(void)
 	return 0;
 }
 
+static inline void db8500_prcmu_system_reset(u16 reset_code) {}
+static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+		bool keep_ap_pll)
+{
+	return 0;
+}
+
+static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
+
+static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
+{
+	return 0;
+}
+
+static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
+{
+	return 0;
+}
+
+static inline int db8500_prcmu_set_display_clocks(void)
+{
+	return 0;
+}
+
+static inline int db8500_prcmu_disable_dsipll(void)
+{
+	return 0;
+}
+
+static inline int db8500_prcmu_enable_dsipll(void)
+{
+	return 0;
+}
 #endif /* CONFIG_UX500_SOC_DB8500 */
 
 #endif /* __MACH_PRCMU_DB8500_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
index 9d28ef9cbc0..5f89152f8b2 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -9,6 +9,7 @@
 #define __MACH_PRCMU_H
 
 #include <linux/interrupt.h>
+#include <asm/mach-types.h>
 #include <mach/prcmu-qos.h>
 
 /* PRCMU Wakeup defines */
@@ -205,13 +206,33 @@ enum ddr_opp {
 
 #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
 
-void __init prcmu_early_init(void);
+static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+		bool keep_ap_pll)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_set_power_state(state, keep_ulp_clk,
+			keep_ap_pll);
+	else
+		return db8500_prcmu_set_power_state(state, keep_ulp_clk,
+			keep_ap_pll);
+}
 
-int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
+static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_set_epod(epod_id, epod_state);
+	else
+		return db8500_prcmu_set_epod(epod_id, epod_state);
+}
 
-int prcmu_set_epod(u16 epod_id, u8 epod_state);
+static inline void prcmu_enable_wakeups(u32 wakeups)
+{
+	if (machine_is_u5500())
+		db5500_prcmu_enable_wakeups(wakeups);
+	else
+		db8500_prcmu_enable_wakeups(wakeups);
+}
 
-void prcmu_enable_wakeups(u32 wakeups);
 static inline void prcmu_disable_wakeups(void)
 {
 	prcmu_enable_wakeups(0);
@@ -222,7 +243,13 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
 
 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
 
-int prcmu_request_clock(u8 clock, bool enable);
+static inline int prcmu_request_clock(u8 clock, bool enable)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_request_clock(clock, enable);
+	else
+		return db8500_prcmu_request_clock(clock, enable);
+}
 
 int prcmu_set_ape_opp(u8 opp);
 int prcmu_get_ape_opp(void);
@@ -231,7 +258,14 @@ int prcmu_get_arm_opp(void);
 int prcmu_set_ddr_opp(u8 opp);
 int prcmu_get_ddr_opp(void);
 
-void prcmu_system_reset(u16 reset_code);
+static inline void prcmu_system_reset(u16 reset_code)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_system_reset(reset_code);
+	else
+		return db8500_prcmu_system_reset(reset_code);
+}
+
 u16 prcmu_get_reset_code(void);
 
 void prcmu_ac_wake_req(void);
@@ -239,13 +273,31 @@ void prcmu_ac_sleep_req(void);
 void prcmu_modem_reset(void);
 bool prcmu_is_ac_wake_requested(void);
 
-int prcmu_set_display_clocks(void);
-int prcmu_disable_dsipll(void);
-int prcmu_enable_dsipll(void);
+static inline int prcmu_set_display_clocks(void)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_set_display_clocks();
+	else
+		return db8500_prcmu_set_display_clocks();
+}
 
-#else
+static inline int prcmu_disable_dsipll(void)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_disable_dsipll();
+	else
+		return db8500_prcmu_disable_dsipll();
+}
 
-static inline void __init prcmu_early_init(void) {}
+static inline int prcmu_enable_dsipll(void)
+{
+	if (machine_is_u5500())
+		return db5500_prcmu_enable_dsipll();
+	else
+		return db8500_prcmu_enable_dsipll();
+}
+
+#else
 
 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
 	bool keep_ap_pll)
@@ -347,4 +399,14 @@ static inline int prcmu_enable_dsipll(void)
 
 #endif
 
+#if defined(CONFIG_UX500_SOC_DB8500)
+
+void __init prcmu_early_init(void);
+
+#else
+
+static inline void __init prcmu_early_init(void) {}
+
+#endif
+
 #endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/prcmu-db5500.c b/arch/arm/mach-ux500/prcmu-db5500.c
index fc6814f9196..63aa600c04b 100644
--- a/arch/arm/mach-ux500/prcmu-db5500.c
+++ b/arch/arm/mach-ux500/prcmu-db5500.c
@@ -327,19 +327,19 @@ unlock_and_return:
 	return r;
 }
 
-void prcmu_enable_wakeups(u32 wakeups)
+void db5500_prcmu_enable_wakeups(u32 wakeups)
 {
 }
 
 /**
- * prcmu_request_clock() - Request for a clock to be enabled or disabled.
+ * db5500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
  * @clock:      The clock for which the request is made.
  * @enable:     Whether the clock should be enabled (true) or disabled (false).
  *
  * This function should only be used by the clock implementation.
  * Do not use it from any other place!
  */
-int prcmu_request_clock(u8 clock, bool enable)
+int db5500_prcmu_request_clock(u8 clock, bool enable)
 {
 	if (clock < PRCMU_NUM_REG_CLOCKS)
 		return request_reg_clock(clock, enable);
@@ -529,7 +529,7 @@ static void ack_dbb_wakeup(void)
 	spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 }
 
-int prcmu_set_epod(u16 epod_id, u8 epod_state)
+int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
 {
 	int r = 0;
 	bool ram_retention = false;
diff --git a/arch/arm/mach-ux500/prcmu-db8500.c b/arch/arm/mach-ux500/prcmu-db8500.c
index 7de5f73f914..d9c4e19785c 100644
--- a/arch/arm/mach-ux500/prcmu-db8500.c
+++ b/arch/arm/mach-ux500/prcmu-db8500.c
@@ -533,7 +533,7 @@ static struct {
 } prcmu_version;
 
 
-int prcmu_enable_dsipll(void)
+int db8500_prcmu_enable_dsipll(void)
 {
 	int i;
 	unsigned int plldsifreq;
@@ -571,7 +571,7 @@ int prcmu_enable_dsipll(void)
 	return 0;
 }
 
-int prcmu_disable_dsipll(void)
+int db8500_prcmu_disable_dsipll(void)
 {
 	/* Disable dsi pll */
 	writel(PRCMU_DISABLE_PLLDSI, (_PRCMU_BASE + PRCM_PLLDSI_ENABLE));
@@ -581,7 +581,7 @@ int prcmu_disable_dsipll(void)
 	return 0;
 }
 
-int prcmu_set_display_clocks(void)
+int db8500_prcmu_set_display_clocks(void)
 {
 	unsigned long flags;
 	unsigned int dsiclk;
@@ -764,7 +764,7 @@ unlock_and_return:
 	return r;
 }
 
-int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
+int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
 {
 	unsigned long flags;
 
@@ -821,7 +821,7 @@ static void config_wakeups(void)
 	last_abb_events = abb_events;
 }
 
-void prcmu_enable_wakeups(u32 wakeups)
+void db8500_prcmu_enable_wakeups(u32 wakeups)
 {
 	unsigned long flags;
 	u32 bits;
@@ -1208,14 +1208,14 @@ out:
 EXPORT_SYMBOL(prcmu_set_hwacc);
 
 /**
- * prcmu_set_epod - set the state of a EPOD (power domain)
+ * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
  * @epod_id: The EPOD to set
  * @epod_state: The new EPOD state
  *
  * This function sets the state of a EPOD (power domain). It may not be called
  * from interrupt context.
  */
-int prcmu_set_epod(u16 epod_id, u8 epod_state)
+int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
 {
 	int r = 0;
 	bool ram_retention = false;
@@ -1427,14 +1427,14 @@ static int request_sga_clock(u8 clock, bool enable)
 }
 
 /**
- * prcmu_request_clock() - Request for a clock to be enabled or disabled.
+ * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
  * @clock:      The clock for which the request is made.
  * @enable:     Whether the clock should be enabled (true) or disabled (false).
  *
  * This function should only be used by the clock implementation.
  * Do not use it from any other place!
  */
-int prcmu_request_clock(u8 clock, bool enable)
+int db8500_prcmu_request_clock(u8 clock, bool enable)
 {
 	if (clock == PRCMU_SGACLK)
 		return request_sga_clock(clock, enable);
@@ -1737,7 +1737,7 @@ bool prcmu_is_ac_wake_requested(void)
  * Saves the reset reason code and then sets the APE_SOFTRST register which
  * fires interrupt to fw
  */
-void prcmu_system_reset(u16 reset_code)
+void db8500_prcmu_system_reset(u16 reset_code)
 {
 	writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
 	writel(1, (_PRCMU_BASE + PRCM_APE_SOFTRST));