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-rwxr-xr-xarch/arm/mach-ux500/clock.c8
-rwxr-xr-xarch/arm/mach-ux500/clock.h3
-rwxr-xr-xarch/arm/mach-ux500/include/mach/mmc.h4
-rw-r--r--drivers/mmc/host/mmc-u8500.c20
4 files changed, 17 insertions, 18 deletions
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 43d6b9e2062..b89be262e03 100755
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -773,9 +773,13 @@ int __init clk_init(void)
+ PRCM_SDMMCCLK_MGT;
unsigned int val;
- /* Switch SDMMCCLK to 52Mhz instead of 104Mhz */
+ /* Set SDMMCCLK at 100Mhz */
val = readl(sdmmclkmgt);
- val = (val & ~0x1f) | 16;
+ /*
+ * set the clock divider
+ * to configure the MCLK at 100MHZ
+ */
+ val = (val & ~SD_CLK_DIV_MASK) | SD_CLK_DIV_VAL;
writel(val, sdmmclkmgt);
} else if (cpu_is_u5500()) {
clk_prcmu_ops.enable = NULL;
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
index 5a454b95886..db5fc107dde 100755
--- a/arch/arm/mach-ux500/clock.h
+++ b/arch/arm/mach-ux500/clock.h
@@ -40,6 +40,9 @@ void update_clk_tree(void);
/* Clock enable bit */
#define ENABLE_BIT 0x100
+#define SD_CLK_DIV_MASK 0x1F
+#define SD_CLK_DIV_VAL 8
+
struct clkops {
void (*enable) (struct clk *);
void (*disable) (struct clk *);
diff --git a/arch/arm/mach-ux500/include/mach/mmc.h b/arch/arm/mach-ux500/include/mach/mmc.h
index a3bdcc35d61..1fa18b8b06d 100755
--- a/arch/arm/mach-ux500/include/mach/mmc.h
+++ b/arch/arm/mach-ux500/include/mach/mmc.h
@@ -327,8 +327,8 @@ struct u8500_mmci_host {
#define MCI_MAXVOLTTRIAL (200) /* 200 times */
#define MAX_FREQ (24000000)
#define MAX_DATA (64*512)
-#define CLK_MAX 50000000
-#define CLK_DIV 0xFF
+#define MMC_HOST_CLK_MAX 100000000
+#define MMC_CLK_DIV 0xFF
/*
* different card states
*/
diff --git a/drivers/mmc/host/mmc-u8500.c b/drivers/mmc/host/mmc-u8500.c
index 5e814fddae1..00875362ec4 100644
--- a/drivers/mmc/host/mmc-u8500.c
+++ b/drivers/mmc/host/mmc-u8500.c
@@ -97,9 +97,9 @@ const int sdio_mode = 0xFFFF;
#endif
#if !defined CONFIG_U8500_MMC_INTR
-static unsigned int fmax = CLK_MAX;
+static unsigned int fmax = MMC_HOST_CLK_MAX;
#else
-static unsigned int fmax = CLK_MAX / 8;
+static unsigned int fmax = MMC_HOST_CLK_MAX / 8;
#endif
#if !defined CONFIG_U8500_MMC_DMA
@@ -1211,12 +1211,6 @@ static void u8500_mmci_start_data(struct u8500_mmci_host *host,
cmd->error = MMC_ERR_NONE;
data->error = MMC_ERR_NONE;
- if (host->devicemode == MCI_POLLINGMODE) {
- temp_reg = readl(base + MMCICLOCK);
- temp_reg = (temp_reg & ~(0xFF)) | ((u8) polling_freq_clk_div & 0xFF);
- writel(0x03, host->base + MMCIPOWER);
- writel(temp_reg, (base + MMCICLOCK));
- }
if (host->devicemode == MCI_DMAMODE)
u8500_mmc_set_dma(host);
@@ -1363,11 +1357,10 @@ static void u8500_mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
break;
}
if (ios->clock) {
- if (ios->clock >= host->mclk)
- clk |= (MCI_CLK_BYPASS | MCI_NEG_EDGE);
+ if (ios->clock >= (host->mclk / 2))
+ clk = 0;
else {
u32 div = host->mclk / ios->clock;
-
if (div > 2) {
clk = div - 2;
if (clk > 255)
@@ -1491,13 +1484,12 @@ static int u8500_mmci_probe(struct amba_device *dev, struct amba_id *id)
}
host = mmc_priv(mmc);
host->oldstat = -1;
- host->mclk = CLK_MAX;
+ host->mclk = MMC_HOST_CLK_MAX;
host->mmc = mmc;
host->board = board;
host->dma_fifo_addr = board->dma_fifo_addr;
host->dma_fifo_dev_type_rx = board->dma_fifo_dev_type_rx;
host->dma_fifo_dev_type_tx = board->dma_fifo_dev_type_tx;
- host->caps = board->caps;
if (board->level_shifter)
host->level_shifter = board->level_shifter;
/**
@@ -1517,7 +1509,7 @@ static int u8500_mmci_probe(struct amba_device *dev, struct amba_id *id)
}
mmc->ops = &u8500_mmci_ops;
mmc->f_max = min(host->mclk, fmax);
- mmc->f_min = CLK_MAX / (CLK_DIV + 2);
+ mmc->f_min = MMC_HOST_CLK_MAX / (MMC_CLK_DIV + 2);
if (devicemode == MCI_DMAMODE)
mmc->caps = host->caps;