u8500: spi: add spi drivers

Signed-off-by: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>

4 files changed, 1386 insertions, 0 deletions

diff --git a/include/linux/spi/spi-stm.h b/include/linux/spi/spi-stm.h
new file mode 100644
index 00000000000..3291132178e
--- /dev/null
+++ b/include/linux/spi/spi-stm.h
@@ -0,0 +1,321 @@
+/*
+ * include/linux/spi/spi-stm.h
+ *
+ * Copyright (C) 2009 STMicroelectronics Pvt. Ltd.
+ *
+ * Author: Sachin Verma <sachin.verma@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SPI_STM_HEADER
+#define SPI_STM_HEADER
+
+/*PUBLIC INTERFACE : To be used by client drivers */
+/**
+ * Protocols supported across different SPI controllers
+ */
+typedef enum {
+	SPI_INTERFACE_MOTOROLA_SPI,	/* Motorola Interface */
+	SPI_INTERFACE_TI_SYNC_SERIAL,	/* Texas Instrument Synch Serial iface*/
+	SPI_INTERFACE_NATIONAL_MICROWIRE,/* National Semiconductor uwire iface*/
+	SPI_INTERFACE_UNIDIRECTIONAL	/* Unidirectional interface */
+} t_spi_interface;
+
+
+
+/*Motorola SPI protocol specific definitions*/
+typedef enum {
+	SPI_CLK_ZERO_CYCLE_DELAY = 0x0,	/* Receive data on rising edge. */
+	SPI_CLK_HALF_CYCLE_DELAY	/* Receive data on falling edge. */
+} t_spi_clk_phase;
+
+/* SPI Clock Polarity */
+typedef enum {
+	SPI_CLK_POL_IDLE_LOW,	/* Low inactive level */
+	SPI_CLK_POL_IDLE_HIGH	/* High inactive level */
+} t_spi_clk_pol;
+
+struct motorola_spi_proto_params {
+	t_spi_clk_phase clk_phase;
+	t_spi_clk_pol clk_pol;
+
+};
+
+
+/* MICROWIRE protocol*/
+/**
+ * Microwire Conrol Lengths Command size in microwire format
+ */
+typedef enum {
+	MWLEN_BITS_4 = 0x03, MWLEN_BITS_5, MWLEN_BITS_6,
+	MWLEN_BITS_7, MWLEN_BITS_8, MWLEN_BITS_9,
+	MWLEN_BITS_10, MWLEN_BITS_11, MWLEN_BITS_12,
+	MWLEN_BITS_13, MWLEN_BITS_14, MWLEN_BITS_15,
+	MWLEN_BITS_16, MWLEN_BITS_17, MWLEN_BITS_18,
+	MWLEN_BITS_19, MWLEN_BITS_20, MWLEN_BITS_21,
+	MWLEN_BITS_22, MWLEN_BITS_23, MWLEN_BITS_24,
+	MWLEN_BITS_25, MWLEN_BITS_26, MWLEN_BITS_27,
+	MWLEN_BITS_28, MWLEN_BITS_29, MWLEN_BITS_30,
+	MWLEN_BITS_31, MWLEN_BITS_32
+} t_microwire_ctrl_len;
+
+/**
+ * Microwire Wait State
+ */
+typedef enum {
+	MWIRE_WAIT_ZERO,/* No wait state inserted after last command bit */
+	MWIRE_WAIT_ONE	/* One wait state inserted after last command bit */
+} t_microwire_wait_state;
+
+/**
+ * Microwire : whether Full/Half Duplex
+ */
+typedef enum {
+	/* SSPTXD becomes bi-directional, SSPRXD not used */
+	MICROWIRE_CHANNEL_FULL_DUPLEX,
+	/* SSPTXD is an output, SSPRXD is an input. */
+	MICROWIRE_CHANNEL_HALF_DUPLEX
+} t_mw_duplex;
+
+
+struct microwire_proto_params {
+	t_microwire_ctrl_len ctrl_len;
+	t_microwire_wait_state wait_state;
+	t_mw_duplex duplex;
+};
+
+/*Common configuration for different SPI controllers*/
+typedef enum {
+	LOOPBACK_DISABLED,
+	LOOPBACK_ENABLED
+} t_spi_loopback;
+
+typedef enum {
+	SPI_MASTER,
+	SPI_SLAVE
+} t_spi_hierarchy;
+
+/*Endianess of FIFO Data */
+typedef enum {
+	SPI_FIFO_MSB,
+	SPI_FIFO_LSB
+} t_spi_fifo_endian;
+
+/**
+ * SPI mode of operation (Communication modes)
+ */
+typedef enum {
+	INTERRUPT_TRANSFER,
+	POLLING_TRANSFER,
+	DMA_TRANSFER
+} t_spi_mode;
+
+/**
+ * CHIP select/deselect commands
+ */
+typedef enum {
+	SPI_CHIP_SELECT,
+	SPI_CHIP_DESELECT
+} t_spi_chip_select;
+
+/**
+ * Type of DMA xfer (between SSP fifo & MEM, or SSP fifo & some device)
+ */
+typedef enum {
+	SPI_WITH_MEM,
+	SPI_WITH_PERIPH
+} t_dma_xfer_type;
+
+struct stm_spi_dma_half_channel_info {
+	enum dma_endianess endianess;
+	enum periph_data_width data_width;
+	enum dma_burst_size burst_size;
+	enum dma_buffer_type buffer_type;
+};
+
+struct stm_spi_dma_pipe_config {
+	union{
+		enum dma_src_dev_type src_dev_type;
+		enum dma_dest_dev_type dst_dev_type;
+	} cli_dev_type;
+	u32 client_fifo_addr;
+	enum dma_xfer_dir dma_dir;
+	struct stm_spi_dma_half_channel_info src_info;
+	struct stm_spi_dma_half_channel_info dst_info;
+};
+
+/**
+ * nmdkspi_dma - DMA configuration for SPI and communicating device
+ * @rx_cfg: DMA configuration of Rx Pipe
+ * @tx_cfg: DMA configuration of Tx Pipe
+ *
+ */
+struct nmdkspi_dma {
+	struct stm_spi_dma_pipe_config rx_cfg;
+	struct stm_spi_dma_pipe_config tx_cfg;
+};
+
+/*#########################################################################*/
+
+/* Private Interface : Not meant for client drivers*/
+
+
+#define SPI_REG_WRITE_BITS(reg, val, mask, sb) \
+		((reg) =   (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
+#define GEN_MASK_BITS(val, mask, sb)  ((u32)((((u32)val)<<(sb)) & (mask)))
+
+/*#######################################################################
+	Message State
+#########################################################################
+ */
+#define START_STATE                     ((void *)0)
+#define RUNNING_STATE                   ((void *)1)
+#define DONE_STATE                      ((void *)2)
+#define ERROR_STATE                     ((void *)-1)
+
+/*CONTROLLER COMMANDS*/
+typedef enum {
+	DISABLE_CONTROLLER  = 0,
+	ENABLE_CONTROLLER ,
+	DISABLE_ALL_INTERRUPT ,
+	ENABLE_ALL_INTERRUPT ,
+	ENABLE_DMA ,
+	DISABLE_DMA ,
+	FLUSH_FIFO ,
+	RESTORE_STATE ,
+	LOAD_DEFAULT_CONFIG ,
+	CLEAR_ALL_INTERRUPT,
+} cntlr_commands;
+
+
+
+/*
+ * Private Driver Data structure used by spi controllers
+ * */
+
+struct driver_data {
+	struct amba_device *adev;
+	struct spi_master *master;
+	struct nmdk_spi_master_cntlr *master_info;
+	void __iomem *regs;
+	struct clk *clk;
+#ifdef CONFIG_SPI_WORKQUEUE
+	struct workqueue_struct *workqueue;
+#endif
+	struct work_struct spi_work;
+	spinlock_t lock;
+	struct list_head queue;
+
+	int busy;
+	int run;
+
+	int dma_ongoing;
+	dmach_t rx_dmach;
+	dmach_t tx_dmach;
+
+	struct tasklet_struct pump_transfers;
+	struct tasklet_struct spi_dma_tasklet;
+	struct timer_list spi_notify_timer;
+	int spi_io_error;
+	struct spi_message *cur_msg;
+	struct spi_transfer *cur_transfer;
+	struct chip_data *cur_chip;
+	void *tx;
+	void *tx_end;
+	void *rx;
+	void *rx_end;
+	void (*write) (struct driver_data *drv_data);
+	void (*read) (struct driver_data *drv_data);
+	void (*delay) (struct driver_data *drv_data);
+	int (*execute_cmd) (struct driver_data *drv_data, int cmd);
+
+	atomic_t dma_cnt;
+};
+
+/***************************************************************************/
+
+struct spi_dma_info{
+	struct stm_dma_pipe_info rx_dma_info;
+	struct stm_dma_pipe_info tx_dma_info;
+};
+
+/**
+ * struct chip_data - To maintain runtime state of SPICntlr for each client chip
+ * @ctr_regs: void pointer which is assigned a struct having regs of the cntlr.
+ * @chip_id: Chip Id assigned to this client to identify it.
+ * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
+ * @enable_dma: Whether to enable DMA or not
+ * @dma_info: Structure holding DMA configuration for the client.
+ * @write: function to be used to write when doing xfer for this chip
+ * @null_write: function to be used for dummy write for receiving data.
+ * @read: function to be used to read when doing xfer for this chip
+ * @null_read: function to be used to for dummy read while writting data.
+ * @cs_control: chip select callback provided by chip
+ * @xfer_type: polling/interrupt/dma
+ *
+ * Runtime state of the SPI controller, maintained per chip,
+ * This would be set according to the current message that would be served
+ */
+struct chip_data {
+	void *ctr_regs;
+	u32 chip_id;
+	u8 n_bytes;
+	u8 enable_dma;
+	struct spi_dma_info *dma_info;
+	void (*write) (struct driver_data *drv_data);
+	void (*null_write) (struct driver_data *drv_data);
+	void (*read) (struct driver_data *drv_data);
+	void (*null_read) (struct driver_data *drv_data);
+	void (*delay) (struct driver_data *drv_data);
+	void (*cs_control) (u32 command);
+	int xfer_type;
+};
+
+/**
+ * struct nmdk_spi_master_cntlr - device.platform_data for SPI cntlr devices.
+ * @num_chipselect: chipselects are used to distinguish individual
+ *      SPI slaves, and are numbered from zero to num_chipselects - 1.
+ *      each slave has a chipselect signal, but it's common that not
+ *      every chipselect is connected to a slave.
+ * @enable_dma: if true enables DMA driven transfers.
+ */
+struct nmdk_spi_master_cntlr {
+	u8 num_chipselect;
+	u8 enable_dma:1;
+	u32 id;
+	u32 base_addr;
+	u32 rx_fifo_addr;
+	u32 tx_fifo_addr;
+	enum dma_src_dev_type rx_fifo_dev_type;
+	enum dma_dest_dev_type tx_fifo_dev_type;
+	gpio_alt_function gpio_alt_func;
+	char *device_name;
+};
+
+/*
+ * Functions declaration
+ **/
+extern void *next_transfer(struct driver_data *drv_data);
+extern void giveback(struct spi_message *message, struct driver_data *drv_data);
+extern void null_cs_control(u32 command);
+extern int stm_spi_transfer(struct spi_device *spi, struct spi_message *msg);
+extern void stm_spi_cleanup(struct spi_device *spi);
+extern int init_queue(struct driver_data *drv_data);
+extern int start_queue(struct driver_data *drv_data);
+extern int stop_queue(struct driver_data *drv_data);
+extern int destroy_queue(struct driver_data *drv_data);
+extern irqreturn_t spi_dma_callback_handler(void *param, int irq);
+extern void stm_spi_tasklet(unsigned long param);
+extern int process_spi_dma_info(struct nmdkspi_dma *dma_config,
+		struct chip_data *chip, void *data);
+
+#endif
diff --git a/include/linux/spi/stm_msp.h b/include/linux/spi/stm_msp.h
new file mode 100644
index 00000000000..e0625a6b9a3
--- /dev/null
+++ b/include/linux/spi/stm_msp.h
@@ -0,0 +1,400 @@
+/*****************************************************************************
+ *  copyright STMicroelectronics, 2007.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2.1 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ *****************************************************************************/
+
+#ifndef NOMADIC_MSP_SPI_HEADER
+#define NOMADIC_MSP_SPI_HEADER
+
+# define DEFAULT_MSP_CLK 48000000
+# define MAX_SCKDIV 1023
+
+#define MSP_FIFO_DEPTH 8
+
+/*#######################################################################
+  MSP Controller Register Offsets
+#########################################################################
+*/
+#define MSP_DR(r)	(r + 0x000)
+#define MSP_GCR(r)	(r + 0x004)
+#define MSP_TCF(r)	(r + 0x008)
+#define MSP_RCF(r)	(r + 0x00C)
+#define MSP_SRG(r)	(r + 0x010)
+#define MSP_FLR(r)	(r + 0x014)
+#define MSP_DMACR(r)	(r + 0x018)
+#define MSP_IMSC(r)	(r + 0x020)
+#define MSP_RIS(r)	(r + 0x024)
+#define MSP_MIS(r)	(r + 0x028)
+#define MSP_ICR(r)	(r + 0x02C)
+#define MSP_MCR(r)	(r + 0x030)
+#define MSP_RCV(r)	(r + 0x034)
+#define MSP_RCM(r)	(r + 0x038)
+#define MSP_TCE0(r)	(r + 0x040)
+#define MSP_TCE1(r)	(r + 0x044)
+#define MSP_TCE2(r)	(r + 0x048)
+#define MSP_TCE3(r)	(r + 0x04C)
+#define MSP_RCE0(r)	(r + 0x060)
+#define MSP_RCE1(r)	(r + 0x064)
+#define MSP_RCE2(r)	(r + 0x068)
+#define MSP_RCE3(r)	(r + 0x06C)
+#define MSP_PID0(r)	(r + 0xFE0)
+#define MSP_PID1(r)	(r + 0xFE4)
+#define MSP_PID2(r)	(r + 0xFE8)
+#define MSP_PID3(r)	(r + 0xFEC)
+
+/*#######################################################################
+  MSP Global Configuration Register - msp_gcr
+#########################################################################
+*/
+#define MSP_GCR_MASK_RXEN		((u32)(0x1UL << 0))
+#define MSP_GCR_MASK_RFFEN		((u32)(0x1UL << 1))
+#define MSP_GCR_MASK_RFSPOL		((u32)(0x1UL << 2))
+#define MSP_GCR_MASK_DCM		((u32)(0x1UL << 3))
+#define MSP_GCR_MASK_RFSSEL		((u32)(0x1UL << 4))
+#define MSP_GCR_MASK_RCKPOL		((u32)(0x1UL << 5))
+#define MSP_GCR_MASK_RCKSEL		((u32)(0x1UL << 6))
+#define MSP_GCR_MASK_LBM		((u32)(0x1UL << 7))
+#define MSP_GCR_MASK_TXEN		((u32)(0x1UL << 8))
+#define MSP_GCR_MASK_TFFEN		((u32)(0x1UL << 9))
+#define MSP_GCR_MASK_TFSPOL		((u32)(0x1UL << 10))
+#define MSP_GCR_MASK_TFSSEL		((u32)(0x3UL << 11))
+#define MSP_GCR_MASK_TCKPOL		((u32)(0x1UL << 13))
+#define MSP_GCR_MASK_TCKSEL		((u32)(0x1UL << 14))
+#define MSP_GCR_MASK_TXDDL		((u32)(0x1UL << 15))
+#define MSP_GCR_MASK_SGEN		((u32)(0x1UL << 16))
+#define MSP_GCR_MASK_SCKPOL		((u32)(0x1UL << 17))
+#define MSP_GCR_MASK_SCKSEL		((u32)(0x3UL << 18))
+#define MSP_GCR_MASK_FGEN		((u32)(0x1UL << 20))
+#define MSP_GCR_MASK_SPICKM		((u32)(0x3UL << 21))
+#define MSP_GCR_MASK_SPIBME		((u32)(0x1UL << 23))
+
+/*#######################################################################
+  MSP Transmit Configuration Register - msp_tcf
+#########################################################################
+*/
+#define MSP_TCF_MASK_TP1ELEN		((u32)(0x7UL << 0))
+#define MSP_TCF_MASK_TP1FLEN		((u32)(0x7FUL << 3))
+#define MSP_TCF_MASK_TDTYP		((u32)(0x3UL << 10))
+#define MSP_TCF_MASK_TENDN		((u32)(0x1UL << 12))
+#define MSP_TCF_MASK_TDDLY		((u32)(0x3UL << 13))
+#define MSP_TCF_MASK_TFSIG		((u32)(0x1UL << 15))
+#define MSP_TCF_MASK_TP2ELEN		((u32)(0x7UL << 16))
+#define MSP_TCF_MASK_TP2FLEN		((u32)(0x7FUL << 19))
+#define MSP_TCF_MASK_TP2SM		((u32)(0x1UL << 26))
+#define MSP_TCF_MASK_TP2EN		((u32)(0x1UL << 27))
+#define MSP_TCF_MASK_TBSWAP		((u32)(0x3UL << 28))
+
+/*#######################################################################
+  MSP Receive Configuration Register - msp_rcf
+#########################################################################
+*/
+#define MSP_RCF_MASK_RP1ELEN		((u32)(0x7UL << 0))
+#define MSP_RCF_MASK_RP1FLEN		((u32)(0x7FUL << 3))
+#define MSP_RCF_MASK_RDTYP		((u32)(0x3UL << 10))
+#define MSP_RCF_MASK_RENDN		((u32)(0x1UL << 12))
+#define MSP_RCF_MASK_RDDLY		((u32)(0x3UL << 13))
+#define MSP_RCF_MASK_RFSIG		((u32)(0x1UL << 15))
+#define MSP_RCF_MASK_RP2ELEN		((u32)(0x7UL << 16))
+#define MSP_RCF_MASK_RP2FLEN		((u32)(0x7FUL << 19))
+#define MSP_RCF_MASK_RP2SM		((u32)(0x1UL << 26))
+#define MSP_RCF_MASK_RP2EN		((u32)(0x1UL << 27))
+#define MSP_RCF_MASK_RBSWAP		((u32)(0x3UL << 28))
+
+/*#######################################################################
+  MSP Sample Rate Generator Register - msp_srg
+#########################################################################
+*/
+#define MSP_SRG_MASK_SCKDIV		((u32)(0x3FFUL << 0))
+#define MSP_SRG_MASK_FRWID		((u32)(0x3FUL << 10))
+#define MSP_SRG_MASK_FRPER		((u32)(0x1FFFUL << 16))
+
+/*#######################################################################
+  MSP Flag Register - msp_flr
+#########################################################################
+*/
+#define MSP_FLR_MASK_RBUSY		((u32)(0x1UL << 0))
+#define MSP_FLR_MASK_RFE		((u32)(0x1UL << 1))
+#define MSP_FLR_MASK_RFU		((u32)(0x1UL << 2))
+#define MSP_FLR_MASK_TBUSY		((u32)(0x1UL << 3))
+#define MSP_FLR_MASK_TFE		((u32)(0x1UL << 4))
+#define MSP_FLR_MASK_TFU		((u32)(0x1UL << 5))
+
+/*#######################################################################
+  MSP DMA Control Register - msp_dmacr
+#########################################################################
+*/
+#define MSP_DMACR_MASK_RDMAE		((u32)(0x1UL << 0))
+#define MSP_DMACR_MASK_TDMAE		((u32)(0x1UL << 1))
+
+/*#######################################################################
+  MSP Interrupt Mask Set/Clear Register - msp_imsc
+#########################################################################
+*/
+#define MSP_IMSC_MASK_RXIM		((u32)(0x1UL << 0))
+#define MSP_IMSC_MASK_ROEIM		((u32)(0x1UL << 1))
+#define MSP_IMSC_MASK_RSEIM		((u32)(0x1UL << 2))
+#define MSP_IMSC_MASK_RFSIM		((u32)(0x1UL << 3))
+#define MSP_IMSC_MASK_TXIM		((u32)(0x1UL << 4))
+#define MSP_IMSC_MASK_TUEIM		((u32)(0x1UL << 5))
+#define MSP_IMSC_MASK_TSEIM		((u32)(0x1UL << 6))
+#define MSP_IMSC_MASK_TFSIM		((u32)(0x1UL << 7))
+#define MSP_IMSC_MASK_RFOIM		((u32)(0x1UL << 8))
+#define MSP_IMSC_MASK_TFOIM		((u32)(0x1UL << 9))
+
+/*#######################################################################
+  MSP Raw Interrupt status Register - msp_ris
+#########################################################################
+*/
+#define MSP_RIS_MASK_RXRIS		((u32)(0x1UL << 0))
+#define MSP_RIS_MASK_ROERIS		((u32)(0x1UL << 1))
+#define MSP_RIS_MASK_RSERIS		((u32)(0x1UL << 2))
+#define MSP_RIS_MASK_RFSRIS		((u32)(0x1UL << 3))
+#define MSP_RIS_MASK_TXRIS		((u32)(0x1UL << 4))
+#define MSP_RIS_MASK_TUERIS		((u32)(0x1UL << 5))
+#define MSP_RIS_MASK_TSERIS		((u32)(0x1UL << 6))
+#define MSP_RIS_MASK_TFSRIS		((u32)(0x1UL << 7))
+#define MSP_RIS_MASK_RFORIS		((u32)(0x1UL << 8))
+#define MSP_RIS_MASK_TFORIS		((u32)(0x1UL << 9))
+
+/*#######################################################################
+  MSP Masked Interrupt status Register - msp_mis
+#########################################################################
+*/
+#define MSP_MIS_MASK_RXMIS		((u32)(0x1UL << 0))
+#define MSP_MIS_MASK_ROEMIS		((u32)(0x1UL << 1))
+#define MSP_MIS_MASK_RSEMIS		((u32)(0x1UL << 2))
+#define MSP_MIS_MASK_RFSMIS		((u32)(0x1UL << 3))
+#define MSP_MIS_MASK_TXMIS		((u32)(0x1UL << 4))
+#define MSP_MIS_MASK_TUEMIS		((u32)(0x1UL << 5))
+#define MSP_MIS_MASK_TSEMIS		((u32)(0x1UL << 6))
+#define MSP_MIS_MASK_TFSMIS		((u32)(0x1UL << 7))
+#define MSP_MIS_MASK_RFOMIS		((u32)(0x1UL << 8))
+#define MSP_MIS_MASK_TFOMIS		((u32)(0x1UL << 9))
+
+/*#######################################################################
+  MSP Interrupt Clear Register - msp_icr
+#########################################################################
+*/
+#define MSP_ICR_MASK_ROEIC		((u32)(0x1UL << 1))
+#define MSP_ICR_MASK_RSEIC		((u32)(0x1UL << 2))
+#define MSP_ICR_MASK_RFSIC		((u32)(0x1UL << 3))
+#define MSP_ICR_MASK_TUEIC		((u32)(0x1UL << 5))
+#define MSP_ICR_MASK_TSEIC		((u32)(0x1UL << 6))
+#define MSP_ICR_MASK_TFSIC		((u32)(0x1UL << 7))
+
+/*#######################################################################
+  MSP Receiver/Transmitter states (Enabled or disabled)
+#########################################################################
+*/
+#define MSP_RECEIVER_DISABLED 0
+#define MSP_RECEIVER_ENABLED 1
+#define MSP_TRANSMITTER_DISABLED 0
+#define MSP_TRANSMITTER_ENABLED 1
+/*#######################################################################
+  MSP Receiver/Transmitter FIFO constants
+#########################################################################
+*/
+#define MSP_LOOPBACK_DISABLED 0
+#define MSP_LOOPBACK_ENABLED 1
+
+#define MSP_TX_FIFO_DISABLED 0
+#define MSP_TX_FIFO_ENABLED 1
+#define MSP_TX_ENDIANESS_MSB	0
+#define MSP_TX_ENDIANESS_LSB	1
+
+#define MSP_RX_FIFO_DISABLED 0
+#define MSP_RX_FIFO_ENABLED 1
+#define MSP_RX_ENDIANESS_MSB	0
+#define MSP_RX_ENDIANESS_LSB	1
+
+
+/*#######################################################################
+  MSP Controller State constants
+#########################################################################
+*/
+#define MSP_IS_SPI_SLAVE 0
+#define MSP_IS_SPI_MASTER 1
+
+#define SPI_BURST_MODE_DISABLE 0
+#define SPI_BURST_MODE_ENABLE 1
+
+/*#######################################################################
+  MSP Phase and Polarity constants
+#########################################################################
+*/
+#define MSP_SPI_PHASE_ZERO_CYCLE_DELAY 0x2
+#define MSP_SPI_PHASE_HALF_CYCLE_DELAY 0x3
+
+#define MSP_TX_CLOCK_POL_LOW 0
+#define MSP_TX_CLOCK_POL_HIGH 1
+
+/*#######################################################################
+  MSP SRG and Frame related constants
+#########################################################################
+*/
+#define MSP_FRAME_GEN_DISABLE 0
+#define MSP_FRAME_GEN_ENABLE 1
+
+#define MSP_SAMPLE_RATE_GEN_DISABLE 0
+#define MSP_SAMPLE_RATE_GEN_ENABLE 1
+
+
+#define MSP_CLOCK_INTERNAL 0x0 /*48 MHz*/
+#define MSP_CLOCK_EXTERNAL 0x2	/*SRG is derived from MSPSCK*/
+/*SRG is derived from MSPSCK pin but is resynchronized on MSPRFS
+ * (Receive Frame Sync signal)*/
+#define MSP_CLOCK_EXTERNAL_RESYNC 0x3
+
+
+#define MSP_TRANSMIT_DATA_WITHOUT_DELAY 0
+#define MSP_TRANSMIT_DATA_WITH_DELAY 1
+
+
+/*INT: means frame sync signal provided by frame generator logic in the MSP
+EXT: means frame sync signal provided by external pin MSPTFS
+*/
+#define MSP_TX_FRAME_SYNC_EXT 0x0
+#define MSP_TX_FRAME_SYNC_INT 0x2
+#define MSP_TX_FRAME_SYNC_INT_CFG 0x3
+
+
+#define MSP_TX_FRAME_SYNC_POL_HIGH 0
+#define MSP_TX_FRAME_SYNC_POL_LOW 1
+
+
+#define MSP_HANDLE_RX_FRAME_SYNC_PULSE 0
+#define MSP_IGNORE_RX_FRAME_SYNC_PULSE 1
+
+#define MSP_RX_NO_DATA_DELAY 0x0
+#define MSP_RX_1BIT_DATA_DELAY 0x1
+#define MSP_RX_2BIT_DATA_DELAY 0x2
+#define MSP_RX_3BIT_DATA_DELAY 0x3
+
+#define MSP_HANDLE_TX_FRAME_SYNC_PULSE 0
+#define MSP_IGNORE_TX_FRAME_SYNC_PULSE 1
+
+#define MSP_TX_NO_DATA_DELAY 0x0
+#define MSP_TX_1BIT_DATA_DELAY 0x1
+#define MSP_TX_2BIT_DATA_DELAY 0x2
+#define MSP_TX_3BIT_DATA_DELAY 0x3
+
+
+/*#######################################################################
+  MSP Interrupt related Macros
+#########################################################################
+*/
+#define DISABLE_ALL_MSP_INTERRUPTS  0x0
+#define ENABLE_ALL_MSP_INTERRUPTS  0x333
+#define CLEAR_ALL_MSP_INTERRUPTS  0xEE
+
+/*#######################################################################
+  Default MSP Register Values
+#########################################################################
+*/
+
+#define DEFAULT_MSP_REG_DMACR 0x00000000
+
+#define DEFAULT_MSP_REG_SRG 0x1FFF0000
+
+#define DEFAULT_MSP_REG_GCR	( \
+	GEN_MASK_BITS(MSP_RECEIVER_DISABLED, MSP_GCR_MASK_RXEN, 0)	|\
+	GEN_MASK_BITS(MSP_RX_FIFO_ENABLED, MSP_GCR_MASK_RFFEN, 1)	|\
+	GEN_MASK_BITS(MSP_LOOPBACK_DISABLED, MSP_GCR_MASK_LBM, 7)	|\
+	GEN_MASK_BITS(MSP_TRANSMITTER_DISABLED, MSP_GCR_MASK_TXEN, 8)	|\
+	GEN_MASK_BITS(MSP_TX_FIFO_ENABLED, MSP_GCR_MASK_TFFEN, 9)	|\
+	GEN_MASK_BITS(MSP_TX_FRAME_SYNC_POL_LOW, MSP_GCR_MASK_TFSPOL, 10)|\
+	GEN_MASK_BITS(MSP_TX_FRAME_SYNC_INT, MSP_GCR_MASK_TFSSEL, 11)	|\
+	GEN_MASK_BITS(MSP_TX_CLOCK_POL_HIGH, MSP_GCR_MASK_TCKPOL, 13)	|\
+	GEN_MASK_BITS(MSP_IS_SPI_MASTER, MSP_GCR_MASK_TCKSEL, 14)	|\
+	GEN_MASK_BITS(MSP_TRANSMIT_DATA_WITHOUT_DELAY, MSP_GCR_MASK_TXDDL, 15)|\
+	GEN_MASK_BITS(MSP_SAMPLE_RATE_GEN_ENABLE, MSP_GCR_MASK_SGEN, 16)|\
+	GEN_MASK_BITS(MSP_CLOCK_INTERNAL, MSP_GCR_MASK_SCKSEL, 18)	|\
+	GEN_MASK_BITS(MSP_FRAME_GEN_ENABLE, MSP_GCR_MASK_FGEN, 20)	|\
+	GEN_MASK_BITS(MSP_SPI_PHASE_ZERO_CYCLE_DELAY, MSP_GCR_MASK_SPICKM, 21)|\
+	GEN_MASK_BITS(SPI_BURST_MODE_DISABLE, MSP_GCR_MASK_SPIBME, 23)\
+	)
+
+#define DEFAULT_MSP_REG_RCF	( \
+	GEN_MASK_BITS(MSP_DATA_BITS_32, MSP_RCF_MASK_RP1ELEN, 0) | \
+	GEN_MASK_BITS(MSP_IGNORE_RX_FRAME_SYNC_PULSE, MSP_RCF_MASK_RFSIG, 15) |\
+	GEN_MASK_BITS(MSP_RX_1BIT_DATA_DELAY, MSP_RCF_MASK_RDDLY, 13) | \
+	GEN_MASK_BITS(MSP_RX_ENDIANESS_LSB, MSP_RCF_MASK_RENDN, 12)  \
+	)
+
+#define DEFAULT_MSP_REG_TCF	( \
+	GEN_MASK_BITS(MSP_DATA_BITS_32, MSP_TCF_MASK_TP1ELEN, 0) | \
+	GEN_MASK_BITS(MSP_IGNORE_TX_FRAME_SYNC_PULSE, MSP_TCF_MASK_TFSIG, 15) |\
+	GEN_MASK_BITS(MSP_TX_1BIT_DATA_DELAY, MSP_TCF_MASK_TDDLY, 13) | \
+	GEN_MASK_BITS(MSP_TX_ENDIANESS_LSB, MSP_TCF_MASK_TENDN, 12)  \
+	)
+
+
+typedef enum {
+	MSP_DATA_BITS_8 = 0x00,
+	MSP_DATA_BITS_10,
+	MSP_DATA_BITS_12,
+	MSP_DATA_BITS_14,
+	MSP_DATA_BITS_16,
+	MSP_DATA_BITS_20,
+	MSP_DATA_BITS_24,
+	MSP_DATA_BITS_32,
+} t_msp_data_size;
+
+typedef enum {
+	MSP_INTERNAL_CLK = 0x0,
+	MSP_EXTERNAL_CLK,
+} t_msp_clk_src;
+
+typedef struct {
+	t_msp_clk_src clk_src;
+	/* value from 0 to 1023 */
+	u16 sckdiv;
+	/*Used only when MSPSCK clocks the sample rate generator (SCKSEL = 1Xb):
+	 * 0b: The rising edge of MSPSCK clocks the sample rate generator
+	 * 1b: The falling edge of MSPSCK clocks the sample rate generator */
+	int sckpol;
+} t_msp_clock_params;
+
+struct msp_controller {
+	t_spi_loopback lbm;
+	t_spi_interface iface;
+	t_spi_hierarchy hierarchy;
+	t_spi_fifo_endian endian_rx;
+	t_spi_fifo_endian endian_tx;
+	t_spi_mode com_mode;
+	t_msp_data_size data_size;
+	t_msp_clock_params clk_freq;
+	int spi_burst_mode_enable;
+	union {
+		struct motorola_spi_proto_params moto;
+		struct microwire_proto_params micro;
+	} proto_params;
+
+	u32 freq;
+	void (*cs_control) (u32 control);
+	t_dma_xfer_type dma_xfer_type;
+	struct nmdkspi_dma *dma_config;
+};
+
+struct msp_regs{
+	u32 gcr;
+	u32 tcf;
+	u32 rcf;
+	u32 srg;
+	u32 dmacr;
+};
+
+#endif
diff --git a/include/linux/spi/stm_spi023.h b/include/linux/spi/stm_spi023.h
new file mode 100644
index 00000000000..7a2aa76a225
--- /dev/null
+++ b/include/linux/spi/stm_spi023.h
@@ -0,0 +1,304 @@
+/*****************************************************************************
+ *  copyright STMicroelectronics, 2007.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2.1 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ *****************************************************************************/
+
+#ifndef STM_SPI023_HEADER
+#define STM_SPI023_HEADER
+
+#define DRIVE_TX			(0)
+#define DO_NOT_DRIVE_TX			(1)
+
+
+#define	SPI_FIFOSIZE  (32)
+#define SPI_FIFOWIDTH (32)
+#define SPI_PERIPHID0 (0x23)
+#define SPI_PERIPHID1 (0x00)
+#define SPI_PERIPHID2 (0x08)
+#define SPI_PERIPHID3 (0x01)
+#define SPI_PCELLID0  (0x0D)
+#define SPI_PCELLID1  (0xF0)
+#define SPI_PCELLID2  (0x05)
+#define SPI_PCELLID3  (0xB1)
+
+/*#######################################################################
+  Macros to access SSP Registers with their offsets
+#########################################################################
+*/
+#define SPI_CR0(r)	(r + 0x000)
+#define SPI_CR1(r)	(r + 0x004)
+#define SPI_DR(r)	(r + 0x008)
+#define SPI_SR(r)	(r + 0x00C)
+#define SPI_CPSR(r)	(r + 0x010)
+#define SPI_IMSC(r)	(r + 0x014)
+#define SPI_RIS(r)	(r + 0x018)
+#define SPI_MIS(r)	(r + 0x01C)
+#define SPI_ICR(r)	(r + 0x020)
+#define SPI_DMACR(r)	(r + 0x024)
+
+
+#define SPI_PID0(r)	(r + 0xFE0)
+#define SPI_PID1(r)	(r + 0xFE4)
+#define SPI_PID2(r)	(r + 0xFE8)
+#define SPI_PID3(r)	(r + 0xFEC)
+
+#define SPI_CID0(r)	(r + 0xFF0)
+#define SPI_CID1(r)	(r + 0xFF4)
+#define SPI_CID2(r)	(r + 0xFF8)
+#define SPI_CID3(r)	(r + 0xFFC)
+
+/*#######################################################################
+  SSP Control Register 0  - SPI_CR0
+#########################################################################
+*/
+#define SPI_CR0_MASK_DSS		((u32)(0x1FUL << 0))
+#define SPI_CR0_MASK_SPO		((u32)(0x1UL << 6))
+#define SPI_CR0_MASK_SPH		((u32)(0x1UL << 7))
+#define SPI_CR0_MASK_SCR		((u32)(0xFFUL << 8))
+
+/*#######################################################################
+  SSP Control Register 0  - SPI_CR1
+#########################################################################
+*/
+#define SPI_CR1_MASK_LBM		((u32)(0x1UL << 0))
+#define SPI_CR1_MASK_SSE		((u32)(0x1UL << 1))
+#define SPI_CR1_MASK_MS			((u32)(0x1UL << 2))
+#define SPI_CR1_MASK_SOD		((u32)(0x1UL << 3))
+#define SPI_CR1_MASK_RENDN		((u32)(0x1UL << 4))
+#define SPI_CR1_MASK_TENDN		((u32)(0x1UL << 5))
+#define SPI_CR1_MASK_MWAIT		((u32)(0x1UL << 6))
+#define SPI_CR1_MASK_RXIFLSEL		((u32)(0x7UL << 7))
+#define SPI_CR1_MASK_TXIFLSEL		((u32)(0x7UL << 10))
+
+/*#######################################################################
+  SSP Data Register  - SPI_dr
+#########################################################################
+*/
+
+#define SPI_DR_MASK_DATA		0xFFFFFFFF
+
+/*#######################################################################
+  SSP Status Register  - SPI_sr
+#########################################################################
+*/
+
+#define SPI_SR_MASK_TFE			((u32)(0x1UL << 0))
+#define SPI_SR_MASK_TNF			((u32)(0x1UL << 1))
+#define SPI_SR_MASK_RNE			((u32)(0x1UL << 2))
+#define SPI_SR_MASK_RFF 		((u32)(0x1UL << 3))
+#define SPI_SR_MASK_BSY			((u32)(0x1UL << 4))
+
+/*#######################################################################
+  SSP Clock Prescale Register  - SPI_cpsr
+#########################################################################
+*/
+#define SPI_CPSR_MASK_CPSDVSR	 	((u32)(0xFFUL << 0))	/*(0xFF << 0)*/
+
+/*#######################################################################
+  SSP Interrupt Mask Set/Clear Register  - SPI_imsc
+#########################################################################
+*/
+#define SPI_IMSC_MASK_RORIM		((u32)(0x1UL << 0))
+#define SPI_IMSC_MASK_RTIM		((u32)(0x1UL << 1))
+#define SPI_IMSC_MASK_RXIM		((u32)(0x1UL << 2))
+#define SPI_IMSC_MASK_TXIM		((u32)(0x1UL << 3))
+
+/*#######################################################################
+  SSP Raw Interrupt Status Register  -  SPI_ris
+#########################################################################
+*/
+#define SPI_RIS_MASK_RORRIS		((u32)(0x1UL << 0))
+#define SPI_RIS_MASK_RTRIS		((u32)(0x1UL << 1))
+#define SPI_RIS_MASK_RXRIS		((u32)(0x1UL << 2))
+#define SPI_RIS_MASK_TXRIS		((u32)(0x1UL << 3))
+
+/*#######################################################################
+  SSP Masked Interrupt Status Register  -  SPI_mis
+#########################################################################
+*/
+
+#define SPI_MIS_MASK_RORMIS		((u32)(0x1UL << 0))
+#define SPI_MIS_MASK_RTMIS		((u32)(0x1UL << 1))
+#define SPI_MIS_MASK_RXMIS		((u32)(0x1UL << 2))
+#define SPI_MIS_MASK_TXMIS		((u32)(0x1UL << 3))
+
+/*#######################################################################
+  SSP Interrupt Clear Register - SPI_icr
+#########################################################################
+*/
+#define SPI_ICR_MASK_RORIC		((u32)(0x1UL << 0))
+#define SPI_ICR_MASK_RTIC		((u32)(0x1UL << 1))
+
+/*#######################################################################
+  SSP DMA Control Register  - SPI_dmacr
+#########################################################################
+*/
+#define SPI_DMACR_MASK_RXDMAE		((u32)(0x1UL << 0))
+#define SPI_DMACR_MASK_TXDMAE		((u32)(0x1UL << 1))
+
+/*#######################################################################
+  SSP State - Whether Enabled or Disabled
+#########################################################################
+*/
+#define SPI_DISABLED 			(0)
+#define SPI_ENABLED 			(1)
+
+/*#######################################################################
+  SSP DMA State - Whether DMA Enabled or Disabled
+#########################################################################
+*/
+#define SPI_DMA_DISABLED 			(0)
+#define SPI_DMA_ENABLED 			(1)
+
+/*#######################################################################
+  SSP Clock Defaults
+#########################################################################
+*/
+
+#define STM_SPI_DEFAULT_CLKRATE 0x2
+#define STM_SPI_DEFAULT_PRESCALE 0x40
+
+/*#######################################################################
+  SSP Clock Parameter ranges
+#########################################################################
+*/
+#define MIN_CPSDVR 0x02
+#define MAX_CPSDVR 0xFE
+#define MIN_SCR 0x00
+#define MAX_SCR 0xFF
+/*#define STM_SPI_CLOCK_FREQ 24000000*/
+#define STM_SPI_CLOCK_FREQ 48000000
+
+/*#######################################################################
+  SSP Interrupt related Macros
+#########################################################################
+*/
+#define DEFAULT_SPI_REG_IMSC  0x0UL
+#define DISABLE_ALL_SPI_INTERRUPTS DEFAULT_SPI_REG_IMSC
+#define ENABLE_ALL_SPI_INTERRUPTS (~DEFAULT_SPI_REG_IMSC)
+
+#define CLEAR_ALL_SPI_INTERRUPTS  0x3
+
+/*#######################################################################
+    Default SSP Register Values
+#########################################################################
+ */
+#define DEFAULT_SPI_REG_CR0	( \
+	GEN_MASK_BITS(SPI_DATA_BITS_12, SPI_CR0_MASK_DSS, 0)	|	\
+	GEN_MASK_BITS(SPI_CLK_POL_IDLE_LOW, SPI_CR0_MASK_SPO, 6) | \
+	GEN_MASK_BITS(SPI_CLK_HALF_CYCLE_DELAY, SPI_CR0_MASK_SPH, 7)	|\
+	GEN_MASK_BITS(STM_SPI_DEFAULT_CLKRATE, SPI_CR0_MASK_SCR, 8)	\
+	)
+
+#define DEFAULT_SPI_REG_CR1	( \
+	GEN_MASK_BITS(LOOPBACK_DISABLED, SPI_CR1_MASK_LBM, 0) | \
+	GEN_MASK_BITS(SPI_DISABLED, SPI_CR1_MASK_SSE, 1) | \
+	GEN_MASK_BITS(SPI_MASTER, SPI_CR1_MASK_MS, 2) | \
+	GEN_MASK_BITS(DO_NOT_DRIVE_TX, SPI_CR1_MASK_SOD, 3) | \
+	GEN_MASK_BITS(SPI_FIFO_MSB, SPI_CR1_MASK_RENDN, 4) | \
+	GEN_MASK_BITS(SPI_FIFO_MSB, SPI_CR1_MASK_TENDN, 5) | \
+	GEN_MASK_BITS(SPI_RX_1_OR_MORE_ELEM, SPI_CR1_MASK_RXIFLSEL, 7) | \
+	GEN_MASK_BITS(SPI_TX_1_OR_MORE_EMPTY_LOC, SPI_CR1_MASK_TXIFLSEL, 10)  \
+	)
+
+#define DEFAULT_SPI_REG_CPSR  (\
+	GEN_MASK_BITS(STM_SPI_DEFAULT_PRESCALE, SPI_CPSR_MASK_CPSDVSR, 0) \
+	)
+
+#define DEFAULT_SPI_REG_DMACR  (\
+		GEN_MASK_BITS(SPI_DMA_DISABLED, SPI_DMACR_MASK_RXDMAE, 0) | \
+		GEN_MASK_BITS(SPI_DMA_DISABLED, SPI_DMACR_MASK_TXDMAE, 1) \
+	)
+
+#define STM_SPICTLR_CLOCK_FREQ 48000000
+
+struct spi023_regs{
+	u32 cr0;
+	u32 cr1;
+	u32 dmacr;
+	u32 cpsr;
+};
+
+
+/**
+ *  * Number of bits in one data element
+ *   */
+typedef enum {
+	SPI_DATA_BITS_4 = 0x03, SPI_DATA_BITS_5, SPI_DATA_BITS_6,
+	SPI_DATA_BITS_7, SPI_DATA_BITS_8, SPI_DATA_BITS_9,
+	SPI_DATA_BITS_10, SPI_DATA_BITS_11, SPI_DATA_BITS_12,
+	SPI_DATA_BITS_13, SPI_DATA_BITS_14, SPI_DATA_BITS_15,
+	SPI_DATA_BITS_16, SPI_DATA_BITS_17, SPI_DATA_BITS_18,
+	SPI_DATA_BITS_19, SPI_DATA_BITS_20, SPI_DATA_BITS_21,
+	SPI_DATA_BITS_22, SPI_DATA_BITS_23, SPI_DATA_BITS_24,
+	SPI_DATA_BITS_25, SPI_DATA_BITS_26, SPI_DATA_BITS_27,
+	SPI_DATA_BITS_28, SPI_DATA_BITS_29, SPI_DATA_BITS_30,
+	SPI_DATA_BITS_31, SPI_DATA_BITS_32
+} t_spi_data_size;
+
+/**
+ * Rx FIFO watermark level which triggers IT: Interrupt fires when _N_ or more
+ * elements in RX FIFO.
+ * */
+typedef enum {
+	SPI_RX_1_OR_MORE_ELEM,
+	SPI_RX_4_OR_MORE_ELEM,
+	SPI_RX_8_OR_MORE_ELEM,
+	SPI_RX_16_OR_MORE_ELEM
+} t_spi_rx_level_trig;
+
+/**
+ * Transmit FIFO watermark level which triggers (IT Interrupt fires
+ * when _N_ or more empty locations in TX FIFO)
+ * */
+typedef enum {
+	SPI_TX_1_OR_MORE_EMPTY_LOC,
+	SPI_TX_4_OR_MORE_EMPTY_LOC,
+	SPI_TX_8_OR_MORE_EMPTY_LOC,
+	SPI_TX_16_OR_MORE_EMPTY_LOC
+} t_spi_tx_level_trig;
+/**
+ *  * Clock parameters, to set SSP clock at a desired freq
+ *   */
+typedef struct {
+	u8 cpsdvsr;             /* value from 2 to 254 (even only!) */
+	u8 scr;         /* value from 0 to 255 */
+} t_spi_clock_params;
+
+
+struct spi023_controller {
+	t_spi_loopback lbm;
+	t_spi_interface iface;
+	t_spi_hierarchy hierarchy;
+	t_spi_fifo_endian endian_rx;
+	t_spi_fifo_endian endian_tx;
+	t_spi_mode com_mode;
+	t_spi_data_size data_size;
+	t_spi_rx_level_trig rx_lev_trig;
+	t_spi_tx_level_trig tx_lev_trig;
+	int slave_tx_disable;
+	t_spi_clock_params clk_freq;
+	union {
+		struct motorola_spi_proto_params moto;
+		struct microwire_proto_params micro;
+	} proto_params;
+
+	u32 freq;
+	void (*cs_control) (u32 control);
+	t_dma_xfer_type dma_xfer_type;
+	struct nmdkspi_dma *dma_config;
+};
+#endif
diff --git a/include/linux/spi/stm_ssp.h b/include/linux/spi/stm_ssp.h
new file mode 100644
index 00000000000..2e5391ba318
--- /dev/null
+++ b/include/linux/spi/stm_ssp.h
@@ -0,0 +1,361 @@
+/*****************************************************************************
+ *  copyright STMicroelectronics, 2007.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2.1 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ *****************************************************************************/
+
+#ifndef STM_SSP_SPI_HEADER
+#define STM_SSP_SPI_HEADER
+
+#define DRIVE_TX			(0)
+#define DO_NOT_DRIVE_TX			(1)
+
+
+#define	SSP_FIFOSIZE  (32)
+#define SSP_FIFOWIDTH (32)
+#define SSP_PERIPHID0 (0x22)
+#define SSP_PERIPHID1 (0x00)
+#define SSP_PERIPHID2 (0x08)
+#define SSP_PERIPHID3 (0x01)
+#define SSP_PCELLID0  (0x0D)
+#define SSP_PCELLID1  (0xF0)
+#define SSP_PCELLID2  (0x05)
+#define SSP_PCELLID3  (0xB1)
+
+/*#######################################################################
+  Macros to access SSP Registers with their offsets
+#########################################################################
+*/
+#define SSP_CR0(r)	(r + 0x000)
+#define SSP_CR1(r)	(r + 0x004)
+#define SSP_DR(r)	(r + 0x008)
+#define SSP_SR(r)	(r + 0x00C)
+#define SSP_CPSR(r)	(r + 0x010)
+#define SSP_IMSC(r)	(r + 0x014)
+#define SSP_RIS(r)	(r + 0x018)
+#define SSP_MIS(r)	(r + 0x01C)
+#define SSP_ICR(r)	(r + 0x020)
+#define SSP_DMACR(r)	(r + 0x024)
+#define SSP_ITCR(r)	(r + 0x080)
+#define SSP_ITIP(r)	(r + 0x084)
+#define SSP_ITOP(r)	(r + 0x088)
+#define SSP_TDR(r)	(r + 0x08C)
+
+#define SSP_PID0(r)	(r + 0xFE0)
+#define SSP_PID1(r)	(r + 0xFE4)
+#define SSP_PID2(r)	(r + 0xFE8)
+#define SSP_PID3(r)	(r + 0xFEC)
+
+#define SSP_CID0(r)	(r + 0xFF0)
+#define SSP_CID1(r)	(r + 0xFF4)
+#define SSP_CID2(r)	(r + 0xFF8)
+#define SSP_CID3(r)	(r + 0xFFC)
+
+/*#######################################################################
+  SSP Control Register 0  - SSP_CR0
+#########################################################################
+*/
+#define SSP_CR0_MASK_DSS		((u32)(0x1FUL << 0))
+#define SSP_CR0_MASK_HALFDUP		((u32)(0x1UL << 5))
+#define SSP_CR0_MASK_SPO		((u32)(0x1UL << 6))
+#define SSP_CR0_MASK_SPH		((u32)(0x1UL << 7))
+#define SSP_CR0_MASK_SCR		((u32)(0xFFUL << 8))
+#define SSP_CR0_MASK_CSS		((u32)(0x1FUL << 16))
+#define SSP_CR0_MASK_FRF		((u32)(0x3UL << 21))
+
+/*#######################################################################
+  SSP Control Register 0  - SSP_CR1
+#########################################################################
+*/
+#define SSP_CR1_MASK_LBM		((u32)(0x1UL << 0))
+#define SSP_CR1_MASK_SSE		((u32)(0x1UL << 1))
+#define SSP_CR1_MASK_MS			((u32)(0x1UL << 2))
+#define SSP_CR1_MASK_SOD		((u32)(0x1UL << 3))
+#define SSP_CR1_MASK_RENDN		((u32)(0x1UL << 4))
+#define SSP_CR1_MASK_TENDN		((u32)(0x1UL << 5))
+#define SSP_CR1_MASK_MWAIT		((u32)(0x1UL << 6))
+#define SSP_CR1_MASK_RXIFLSEL		((u32)(0x7UL << 7))
+#define SSP_CR1_MASK_TXIFLSEL		((u32)(0x7UL << 10))
+
+/*#######################################################################
+  SSP Data Register  - ssp_dr
+#########################################################################
+*/
+
+#define SSP_DR_MASK_DATA		0xFFFFFFFF
+
+/*#######################################################################
+  SSP Status Register  - ssp_sr
+#########################################################################
+*/
+
+#define SSP_SR_MASK_TFE		((u32)(0x1UL << 0))	/* Tx FIFO empty */
+#define SSP_SR_MASK_TNF		((u32)(0x1UL << 1))	/* Tx FIFO not full */
+#define SSP_SR_MASK_RNE		((u32)(0x1UL << 2))	/* Rx FIFO not empty */
+#define SSP_SR_MASK_RFF 	((u32)(0x1UL << 3))	/* Rx FIFO full */
+#define SSP_SR_MASK_BSY		((u32)(0x1UL << 4))	/* Busy Flag */
+
+/*#######################################################################
+  SSP Clock Prescale Register  - ssp_cpsr
+#########################################################################
+*/
+#define SSP_CPSR_MASK_CPSDVSR	 	((u32)(0xFFUL << 0))	/*(0xFF << 0)*/
+
+/*#######################################################################
+  SSP Interrupt Mask Set/Clear Register  - ssp_imsc
+#########################################################################
+*/
+#define SSP_IMSC_MASK_RORIM		((u32)(0x1UL << 0))
+#define SSP_IMSC_MASK_RTIM		((u32)(0x1UL << 1))
+#define SSP_IMSC_MASK_RXIM		((u32)(0x1UL << 2))
+#define SSP_IMSC_MASK_TXIM		((u32)(0x1UL << 3))
+
+/*#######################################################################
+  SSP Raw Interrupt Status Register  -  ssp_ris
+#########################################################################
+*/
+#define SSP_RIS_MASK_RORRIS		((u32)(0x1UL << 0))
+#define SSP_RIS_MASK_RTRIS		((u32)(0x1UL << 1))
+#define SSP_RIS_MASK_RXRIS		((u32)(0x1UL << 2))
+#define SSP_RIS_MASK_TXRIS		((u32)(0x1UL << 3))
+
+/*#######################################################################
+  SSP Masked Interrupt Status Register  -  ssp_mis
+#########################################################################
+*/
+
+#define SSP_MIS_MASK_RORMIS		((u32)(0x1UL << 0))
+#define SSP_MIS_MASK_RTMIS		((u32)(0x1UL << 1))
+#define SSP_MIS_MASK_RXMIS		((u32)(0x1UL << 2))
+#define SSP_MIS_MASK_TXMIS		((u32)(0x1UL << 3))
+
+/*#######################################################################
+  SSP Interrupt Clear Register - ssp_icr
+#########################################################################
+*/
+#define SSP_ICR_MASK_RORIC		((u32)(0x1UL << 0))
+#define SSP_ICR_MASK_RTIC		((u32)(0x1UL << 1))
+
+/*#######################################################################
+  SSP DMA Control Register  - ssp_dmacr
+#########################################################################
+*/
+#define SSP_DMACR_MASK_RXDMAE		((u32)(0x1UL << 0))
+#define SSP_DMACR_MASK_TXDMAE		((u32)(0x1UL << 1))
+
+/*#######################################################################
+  SSP Integration Test control Register  - ssp_itcr
+#########################################################################
+*/
+#define SSP_ITCR_MASK_ITEN		((u32)(0x1UL << 0))
+#define SSP_ITCR_MASK_TESTFIFO		((u32)(0x1UL << 1))
+
+/*#######################################################################
+  SSP Integration Test Input Register  - ssp_itip
+#########################################################################
+*/
+#define ITIP_MASK_SSPRXD		 ((u32)(0x1UL << 0))
+#define ITIP_MASK_SSPFSSIN		 ((u32)(0x1UL << 1))
+#define ITIP_MASK_SSPCLKIN		 ((u32)(0x1UL << 2))
+#define ITIP_MASK_RXDMAC		 ((u32)(0x1UL << 3))
+#define ITIP_MASK_TXDMAC		 ((u32)(0x1UL << 4))
+#define ITIP_MASK_SSPTXDIN		 ((u32)(0x1UL << 5))
+
+/*#######################################################################
+  SSP Integration Test output Register  - ssp_itop
+#########################################################################
+*/
+#define ITOP_MASK_SSPTXD		 ((u32)(0x1UL << 0))
+#define ITOP_MASK_SSPFSSOUT		 ((u32)(0x1UL << 1))
+#define ITOP_MASK_SSPCLKOUT		 ((u32)(0x1UL << 2))
+#define ITOP_MASK_SSPOEn		 ((u32)(0x1UL << 3))
+#define ITOP_MASK_SSPCTLOEn		 ((u32)(0x1UL << 4))
+#define ITOP_MASK_RORINTR		 ((u32)(0x1UL << 5))
+#define ITOP_MASK_RTINTR		 ((u32)(0x1UL << 6))
+#define ITOP_MASK_RXINTR		 ((u32)(0x1UL << 7))
+#define ITOP_MASK_TXINTR		 ((u32)(0x1UL << 8))
+#define ITOP_MASK_INTR			 ((u32)(0x1UL << 9))
+#define ITOP_MASK_RXDMABREQ		 ((u32)(0x1UL << 10))
+#define ITOP_MASK_RXDMASREQ		 ((u32)(0x1UL << 11))
+#define ITOP_MASK_TXDMABREQ		 ((u32)(0x1UL << 12))
+#define ITOP_MASK_TXDMASREQ		 ((u32)(0x1UL << 13))
+
+/*#######################################################################
+  SSP Test Data Register  - ssp_tdr
+#########################################################################
+*/
+#define TDR_MASK_TESTDATA 		(0xFFFFFFFF)
+
+/*#######################################################################
+  SSP State - Whether Enabled or Disabled
+#########################################################################
+*/
+#define SSP_DISABLED 			(0)
+#define SSP_ENABLED 			(1)
+
+/*#######################################################################
+  SSP DMA State - Whether DMA Enabled or Disabled
+#########################################################################
+*/
+#define SSP_DMA_DISABLED 			(0)
+#define SSP_DMA_ENABLED 			(1)
+
+/*#######################################################################
+  SSP Clock Defaults
+#########################################################################
+*/
+
+#define STM_SSP_DEFAULT_CLKRATE 0x2
+#define STM_SSP_DEFAULT_PRESCALE 0x40
+
+/*#######################################################################
+  SSP Clock Parameter ranges
+#########################################################################
+*/
+#define MIN_CPSDVR 0x02
+#define MAX_CPSDVR 0xFE
+#define MIN_SCR 0x00
+#define MAX_SCR 0xFF
+/*#define STM_SSP_CLOCK_FREQ 24000000*/
+#define STM_SSP_CLOCK_FREQ 48000000
+
+/*#######################################################################
+  SSP Interrupt related Macros
+#########################################################################
+*/
+#define DEFAULT_SSP_REG_IMSC  0x0UL
+#define DISABLE_ALL_SSP_INTERRUPTS DEFAULT_SSP_REG_IMSC
+#define ENABLE_ALL_SSP_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
+
+#define CLEAR_ALL_SSP_INTERRUPTS  0x3
+
+/*#######################################################################
+  Default SSP Register Values
+#########################################################################
+*/
+#define DEFAULT_SSP_REG_CR0	( \
+	GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0)	|	\
+	GEN_MASK_BITS(MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP, 5)|\
+	GEN_MASK_BITS(SPI_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
+	GEN_MASK_BITS(SPI_CLK_HALF_CYCLE_DELAY, SSP_CR0_MASK_SPH, 7)	|\
+	GEN_MASK_BITS(STM_SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8)	|\
+	GEN_MASK_BITS(MWLEN_BITS_8, SSP_CR0_MASK_CSS, 16)	|\
+	GEN_MASK_BITS(SPI_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 21)  \
+		)
+
+#define DEFAULT_SSP_REG_CR1	( \
+	GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
+	GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
+	GEN_MASK_BITS(SPI_MASTER, SSP_CR1_MASK_MS, 2) | \
+	GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
+	GEN_MASK_BITS(SPI_FIFO_MSB, SSP_CR1_MASK_RENDN, 4) | \
+	GEN_MASK_BITS(SPI_FIFO_MSB, SSP_CR1_MASK_TENDN, 5) | \
+	GEN_MASK_BITS(MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT, 6) |\
+	GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL, 7) | \
+	GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL, 10)  \
+		)
+
+#define DEFAULT_SSP_REG_CPSR  (\
+	GEN_MASK_BITS(STM_SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
+		)
+
+#define DEFAULT_SSP_REG_DMACR  (\
+	GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
+	GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
+		)
+
+#ifdef __KERNEL__
+struct ssp_regs{
+	u32 cr0;
+	u32 cr1;
+	u32 dmacr;
+	u32 cpsr;
+};
+
+
+/**
+ * Number of bits in one data element
+ */
+typedef enum {
+	SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
+	SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
+	SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
+	SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
+	SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
+	SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
+	SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
+	SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
+	SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
+	SSP_DATA_BITS_31, SSP_DATA_BITS_32
+} t_ssp_data_size;
+
+/**
+ * Rx FIFO watermark level which triggers IT: Interrupt fires when _N_ or more
+ * elements in RX FIFO.
+ */
+typedef enum {
+	SSP_RX_1_OR_MORE_ELEM,
+	SSP_RX_4_OR_MORE_ELEM,
+	SSP_RX_8_OR_MORE_ELEM,
+	SSP_RX_16_OR_MORE_ELEM,
+	SSP_RX_32_OR_MORE_ELEM
+} t_ssp_rx_level_trig;
+
+/**
+ * Tx FIFO watermark level which triggers (IT Interrupt fires
+ * when _N_ or more empty locations in TX FIFO)
+ */
+typedef enum {
+	SSP_TX_1_OR_MORE_EMPTY_LOC,
+	SSP_TX_4_OR_MORE_EMPTY_LOC,
+	SSP_TX_8_OR_MORE_EMPTY_LOC,
+	SSP_TX_16_OR_MORE_EMPTY_LOC,
+	SSP_TX_32_OR_MORE_EMPTY_LOC
+} t_ssp_tx_level_trig;
+
+/**
+ * Clock parameters, to set SSP clock at a desired freq
+ */
+typedef struct {
+	u8 cpsdvsr;		/* value from 2 to 254 (even only!) */
+	u8 scr;		/* value from 0 to 255 */
+} t_ssp_clock_params;
+
+struct ssp_controller {
+	t_spi_loopback lbm;
+	t_spi_interface iface;
+	t_spi_hierarchy hierarchy;
+	t_spi_fifo_endian endian_rx;
+	t_spi_fifo_endian endian_tx;
+	t_spi_mode com_mode;
+	t_ssp_data_size data_size;
+	t_ssp_rx_level_trig rx_lev_trig;
+	t_ssp_tx_level_trig tx_lev_trig;
+	int slave_tx_disable;
+	t_ssp_clock_params clk_freq;
+
+	union {
+		struct motorola_spi_proto_params moto;
+		struct microwire_proto_params micro;
+	} proto_params;
+
+	u32 freq;
+	void (*cs_control) (u32 control);
+	t_dma_xfer_type dma_xfer_type;
+	struct nmdkspi_dma *dma_config;
+};
+
+#endif
+#endif