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authorMartin Schwidefsky <schwidefsky@de.ibm.com>2008-01-26 14:10:58 +0100
committerMartin Schwidefsky <schwidefsky@de.ibm.com>2008-01-26 14:11:10 +0100
commit6f457e1a149eb39ee58d51913e8023fc27c52806 (patch)
treed702ec38780667a3305e45df05c4f7df3730e9f6 /arch
parent4b28a8fe78bd593cdc4454cf28af71ca9556914d (diff)
[S390] Fix tlb flushing with idte.
The clear-by-asce operation of the idte instruction gets an asce (address-space-control-element) as argument to specify which TLBs need to get flushed. The current code passes a plain pointer to the start of the pgd without the additional bits which would make the pointer an asce. The current machines don't mind the difference but a future model might want to use the designation type control bits in the asce as a filter for the TLBs to flush. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/s390/kernel/head64.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index a87b1976d40..79dccd206a6 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -157,7 +157,7 @@ startup_continue:
.long 0xb2b10000 # store facility list
tm 0xc8,0x08 # check bit for clearing-by-ASCE
bno 0f-.LPG1(%r13)
- lhi %r1,2094
+ lhi %r1,2048
lhi %r2,0
.long 0xb98e2001
oi 7(%r12),0x80 # set IDTE flag