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authorChris Zankel <chris@zankel.net>2008-02-12 13:10:40 -0800
committerChris Zankel <chris@zankel.net>2008-02-13 17:24:17 -0800
commit03dfa442e5aaf644bb9b3b506abbd76786867eb1 (patch)
tree32811e80cb896774b7a0d88f73c3f774332183c2 /arch/xtensa
parent3b4a49e21b0d8a69629623815a8caff3eb4cf9f7 (diff)
[XTENSA] Remove unused code
We will never (need to) support signal handling coming from a double exception. There are too many things that could go wrong and delivering signals is not the fastest method for IPC, anyway. Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/kernel/entry.S22
1 files changed, 0 insertions, 22 deletions
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index b4b14a579a3..b51ddb0dcf2 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -28,7 +28,6 @@
/* Unimplemented features. */
-#undef SIGNAL_HANDLING_IN_DOUBLE_EXCEPTION
#undef KERNEL_STACK_OVERFLOW_CHECK
#undef PREEMPTIBLE_KERNEL
#undef ALLOCA_EXCEPTION_IN_IRAM
@@ -431,11 +430,8 @@ common_exception_return:
_bbsi.l a4, TIF_NEED_RESCHED, 3f
_bbci.l a4, TIF_SIGPENDING, 4f
-#ifndef SIGNAL_HANDLING_IN_DOUBLE_EXCEPTION
l32i a4, a1, PT_DEPC
bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
-#endif
-
/* Reenable interrupts and call do_signal() */
wsr a3, PS
@@ -1247,16 +1243,6 @@ fast_syscall_spill_registers_fixup:
* Note: This frame might be the same as above.
*/
-#ifdef SIGNAL_HANDLING_IN_DOUBLE_EXCEPTION
- /* Restore registers we precautiously saved.
- * We have the value of the 'right' a3
- */
-
- l32i a7, a2, PT_AREG5
- l32i a11, a2, PT_AREG6
- l32i a15, a2, PT_AREG7
-#endif
-
/* Setup stack pointer. */
addi a2, a2, -PT_USER_SIZE
@@ -1290,14 +1276,6 @@ fast_syscall_spill_registers_fixup_return:
s32i a2, a3, EXC_TABLE_PARAM
l32i a2, a3, EXC_TABLE_KSTK
-#ifdef SIGNAL_HANDLING_IN_DOUBLE_EXCEPTION
- /* Save registers again that might be clobbered. */
-
- s32i a7, a2, PT_AREG5
- s32i a11, a2, PT_AREG6
- s32i a15, a2, PT_AREG7
-#endif
-
/* Load WB at the time the exception occurred. */
rsr a3, SAR # WB is still in SAR