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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-02-15 21:20:18 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-02-15 21:20:18 +0000
commit56012808f4d5606e401539f663d92009d964425b (patch)
treef3736a97725647393a2db7c95462d857115197ca /arch/arm/include
parenta814290e17ae314bd614476cffc6119846eca27e (diff)
parentb2a731aa5cbca7e0252da75e16de7ae5feb1313a (diff)
Merge branch 'for-rmk' of git://git.marvell.com/orion into devel-stable
Conflicts: arch/arm/Makefile
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/cacheflush.h20
1 files changed, 17 insertions, 3 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 730aefcfbee..c77d2fa1f6e 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -154,16 +154,16 @@
* Please note that the implementation of these, and the required
* effects are cache-type (VIVT/VIPT/PIPT) specific.
*
- * flush_cache_kern_all()
+ * flush_kern_all()
*
* Unconditionally clean and invalidate the entire cache.
*
- * flush_cache_user_mm(mm)
+ * flush_user_all()
*
* Clean and invalidate all user space cache entries
* before a change of page tables.
*
- * flush_cache_user_range(start, end, flags)
+ * flush_user_range(start, end, flags)
*
* Clean and invalidate a range of cache entries in the
* specified address space before a change of page tables.
@@ -179,6 +179,20 @@
* - start - virtual start address
* - end - virtual end address
*
+ * coherent_user_range(start, end)
+ *
+ * Ensure coherency between the Icache and the Dcache in the
+ * region described by start, end. If you have non-snooping
+ * Harvard caches, you need to implement this function.
+ * - start - virtual start address
+ * - end - virtual end address
+ *
+ * flush_kern_dcache_area(kaddr, size)
+ *
+ * Ensure that the data held in page is written back.
+ * - kaddr - page address
+ * - size - region size
+ *
* DMA Cache Coherency
* ===================
*