|author||Santosh Shilimkar <email@example.com>||2010-02-04 19:42:42 +0100|
|committer||Russell King <firstname.lastname@example.org>||2010-02-15 21:39:55 +0000|
ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate clean lines
This patch implements the work-around for the errata 588369.The secure API is used to alter L2 debug register because of trust-zone. This version updated with comments from Russell and Catalin and generated against 2.6.33-rc6 mainline kernel. Detail comments can be found: http://www.spinics.net/lists/linux-omap/msg23431.html Signed-off-by: Woodruff Richard <email@example.com> Signed-off-by: Santosh Shilimkar <firstname.lastname@example.org> Acked-by: Catalin Marinas <email@example.com> Acked-by: Tony Lindgren <firstname.lastname@example.org> Signed-off-by: Russell King <email@example.com>
Diffstat (limited to 'arch/arm/Kconfig')
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 762ae536f90..0f1ad743ccd 100644
@@ -924,6 +924,19 @@ config ARM_ERRATA_460075
ACTLR register. Note that setting specific bits in the ACTLR register
may not be available in non-secure mode.
+ bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
+ depends on CACHE_L2X0 && ARCH_OMAP4
+ The PL310 L2 cache controller implements three types of Clean &
+ Invalidate maintenance operations: by Physical Address
+ (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+ They are architecturally defined to behave as the execution of a
+ clean operation followed immediately by an invalidate operation,
+ both performing to the same memory location. This functionality
+ is not correctly implemented in PL310 as clean lines are not
+ invalidated as a result of these operations. Note that this errata
+ uses Texas Instrument's secure monitor api.