diff options
| author | Anson Huang <b20788@freescale.com> | 2011-11-16 14:04:41 +0800 |
|---|---|---|
| committer | Eric Miao <eric.miao@linaro.org> | 2011-12-01 11:36:35 +0800 |
| commit | 3659593545186ddcd1ad2e1cda8c23d7f1b5f269 (patch) | |
| tree | 840c77f7405d9e4ca4aee0130c63a29e7e35a359 /arch | |
| parent | aa3e42d091076bc46077413b9b7848915cfa6a93 (diff) | |
ENGR00162330 [mx6]Only mask irq#86 and #125 for wait mode
These two irqs can't be masked together, otherwise, system
will crash when only booting up one core, and NFS can only
work with 4 cores running. Need hardware team to help find
the root cause, this is only a temp work around.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-mx6/irq.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/mach-mx6/irq.c b/arch/arm/mach-mx6/irq.c index 2c7fbf026df..3d8f81bb6e2 100644 --- a/arch/arm/mach-mx6/irq.c +++ b/arch/arm/mach-mx6/irq.c @@ -26,6 +26,7 @@ int mx6q_register_gpios(void); unsigned int gpc_wake_irq[4]; +extern bool enable_wait_mode; static int mx6_gic_irq_set_wake(struct irq_data *d, unsigned int enable) { @@ -60,9 +61,11 @@ void mx6_init_irq(void) gic_init(0, 29, IO_ADDRESS(IC_DISTRIBUTOR_BASE_ADDR), IO_ADDRESS(IC_INTERFACES_BASE_ADDR)); - /* Mask the always pending interrupts - HW bug. */ - __raw_writel(0x00400000, gpc_base + 0x0c); - __raw_writel(0x20000000, gpc_base + 0x10); + if (enable_wait_mode) { + /* Mask the always pending interrupts - HW bug. */ + __raw_writel(0x00400000, gpc_base + 0x0c); + __raw_writel(0x20000000, gpc_base + 0x10); + } for (i = MXC_INT_START; i <= MXC_INT_END; i++) { desc = irq_to_desc(i); |