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authorRanjani Vaidyanathan <ra5478@freescale.com>2011-11-04 16:19:19 -0500
committerEric Miao <eric.miao@canonical.com>2011-11-10 07:39:07 +0800
commitaaae26e5a7f1d54ae768b4d1efa79602faf5a48d (patch)
treec83c158c2225da92ec41e24e8009ca4381c3506f
parentc1773f52758dc09e037087b39f3cfc6a47d2f5a8 (diff)
ENGR00161487: Fix SD/USB/FEC performance issue.er3-preview
When WAIT mode is not enabled, execute cpu_do_idle() code. Currently WAIT mode requires the code to be run from IRAM with caches disabled. No L2 cache access should be done for a specified period after the system exits WAIT mode. This delay and running code from IRAM adversely affects the SDHC performance. Hardware team is looking into the extended delay that is required. Till its root caused, default should be to execute cpu_do_idle() and disable entry into WAIT mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
-rw-r--r--arch/arm/mach-mx6/cpu.c2
-rw-r--r--arch/arm/mach-mx6/system.c11
2 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c
index 0e85d925dfd..0833b574c30 100644
--- a/arch/arm/mach-mx6/cpu.c
+++ b/arch/arm/mach-mx6/cpu.c
@@ -37,7 +37,7 @@ extern void mx6_wait(void);
struct cpu_op *(*get_cpu_op)(int *op);
static void __iomem *arm_base = IO_ADDRESS(MX6Q_A9_PLATFRM_BASE);
-static bool enable_wait_mode;
+bool enable_wait_mode;
void __iomem *gpc_base;
void __iomem *ccm_base;
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c
index db1dea5b74d..418e23e1bde 100644
--- a/arch/arm/mach-mx6/system.c
+++ b/arch/arm/mach-mx6/system.c
@@ -54,6 +54,7 @@ static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
extern void (*mx6_wait_in_iram)(void *ccm_base);
extern void mx6_wait(void);
extern void *mx6_wait_in_iram_base;
+extern bool enable_wait_mode;
void gpc_set_wakeup(unsigned int irq[4])
{
@@ -144,10 +145,12 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
void arch_idle(void)
{
- if ((num_online_cpus() == num_present_cpus())
- && mx6_wait_in_iram != NULL) {
- mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
- mx6_wait_in_iram(MXC_CCM_BASE);
+ if (enable_wait_mode) {
+ if ((num_online_cpus() == num_present_cpus())
+ && mx6_wait_in_iram != NULL) {
+ mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+ mx6_wait_in_iram(MXC_CCM_BASE);
+ }
} else
cpu_do_idle();
}