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path: root/arch/blackfin/cpu/cache.S
blob: 6ed655a674f52c8c3297c9cbb7db21c02c3d3f9c (plain)
 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87  /* * Blackfin cache control code * * Copyright 2003-2008 Analog Devices Inc. * * Enter bugs at http://blackfin.uclinux.org/ * * Licensed under the GPL-2 or later. */ #include #include #include .text /* Since all L1 caches work the same way, we use the same method for flushing * them. Only the actual flush instruction differs. We write this in asm as * GCC can be hard to coax into writing nice hardware loops. * * Also, we assume the following register setup: * R0 = start address * R1 = end address */ .macro do_flush flushins:req optflushins optnopins label R2 = -L1_CACHE_BYTES; /* start = (start & -L1_CACHE_BYTES) */ R0 = R0 & R2; /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ R1 += -1; R1 = R1 & R2; R1 += L1_CACHE_BYTES; /* count = (end - start) >> L1_CACHE_SHIFT */ R2 = R1 - R0; R2 >>= L1_CACHE_SHIFT; P1 = R2; .ifnb \label \label : .endif P0 = R0; LSETUP (1f, 2f) LC1 = P1; 1: .ifnb \optflushins \optflushins [P0]; .endif #if ANOMALY_05000443 .ifb \optnopins 2: .endif \flushins [P0++]; .ifnb \optnopins 2: \optnopins; .endif #else 2: \flushins [P0++]; #endif RTS; .endm /* Invalidate all instruction cache lines assocoiated with this memory area */ ENTRY(_blackfin_icache_flush_range) do_flush IFLUSH, , nop ENDPROC(_blackfin_icache_flush_range) /* Flush all cache lines assocoiated with this area of memory. */ ENTRY(_blackfin_icache_dcache_flush_range) do_flush FLUSH, IFLUSH ENDPROC(_blackfin_icache_dcache_flush_range) /* Throw away all D-cached data in specified region without any obligation to * write them back. Since the Blackfin ISA does not have an "invalidate" * instruction, we use flush/invalidate. Perhaps as a speed optimization we * could bang on the DTEST MMRs ... */ ENTRY(_blackfin_dcache_flush_invalidate_range) do_flush FLUSHINV ENDPROC(_blackfin_dcache_flush_invalidate_range) /* Flush all data cache lines assocoiated with this memory area */ ENTRY(_blackfin_dcache_flush_range) do_flush FLUSH, , , .Ldfr ENDPROC(_blackfin_dcache_flush_range)