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authorPeter Tyser <ptyser@xes-inc.com>2010-04-12 22:28:16 -0500
committerWolfgang Denk <wd@denx.de>2010-04-13 09:13:26 +0200
commit6260fb0458d94c83aa5b180745b1946c0c94d364 (patch)
treee48fdfbfc874a78b22f6e0b914a7661e42a7e15f /arch/microblaze/cpu
parent8a15c2d10b0b784f0cfba1240f06a4d933b975fa (diff)
downloadu-boot-linaro-stable-6260fb0458d94c83aa5b180745b1946c0c94d364.tar.gz
microblaze: Move cpu/microblaze/* to arch/microblaze/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'arch/microblaze/cpu')
-rw-r--r--arch/microblaze/cpu/Makefile48
-rw-r--r--arch/microblaze/cpu/cache.c62
-rw-r--r--arch/microblaze/cpu/cpu.c25
-rw-r--r--arch/microblaze/cpu/exception.c74
-rw-r--r--arch/microblaze/cpu/interrupts.c220
-rw-r--r--arch/microblaze/cpu/irq.S172
-rw-r--r--arch/microblaze/cpu/start.S150
-rw-r--r--arch/microblaze/cpu/timer.c73
8 files changed, 824 insertions, 0 deletions
diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile
new file mode 100644
index 000000000..9d542013c
--- /dev/null
+++ b/arch/microblaze/cpu/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+START = start.o
+SOBJS = irq.o
+COBJS = cpu.o interrupts.o cache.o exception.o timer.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
new file mode 100644
index 000000000..3b7c4d4f7
--- /dev/null
+++ b/arch/microblaze/cpu/cache.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/asm.h>
+
+int dcache_status (void)
+{
+ int i = 0;
+ int mask = 0x80;
+ __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
+ /* i&=0x80 */
+ __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
+ return i;
+}
+
+int icache_status (void)
+{
+ int i = 0;
+ int mask = 0x20;
+ __asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
+ /* i&=0x20 */
+ __asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
+ return i;
+}
+
+void icache_enable (void) {
+ MSRSET(0x20);
+}
+
+void icache_disable(void) {
+ MSRCLR(0x20);
+}
+
+void dcache_enable (void) {
+ MSRSET(0x80);
+}
+
+void dcache_disable(void) {
+ MSRCLR(0x80);
+}
diff --git a/arch/microblaze/cpu/cpu.c b/arch/microblaze/cpu/cpu.c
new file mode 100644
index 000000000..4d2b270b2
--- /dev/null
+++ b/arch/microblaze/cpu/cpu.c
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* EMPTY FILE */
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
new file mode 100644
index 000000000..0365de3a0
--- /dev/null
+++ b/arch/microblaze/cpu/exception.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/asm.h>
+
+void _hw_exception_handler (void)
+{
+ int address = 0;
+ int state = 0;
+ /* loading address of exception EAR */
+ MFS (address, rear);
+ /* loading excetpion state register ESR */
+ MFS (state, resr);
+ printf ("Hardware exception at 0x%x address\n", address);
+ switch (state & 0x1f) { /* mask on exception cause */
+ case 0x1:
+ puts ("Unaligned data access exception\n");
+ break;
+ case 0x2:
+ puts ("Illegal op-code exception\n");
+ break;
+ case 0x3:
+ puts ("Instruction bus error exception\n");
+ break;
+ case 0x4:
+ puts ("Data bus error exception\n");
+ break;
+ case 0x5:
+ puts ("Divide by zero exception\n");
+ break;
+#ifdef MICROBLAZE_V5
+ case 0x1000:
+ puts ("Exception in delay slot\n");
+ break;
+#endif
+ default:
+ puts ("Undefined cause\n");
+ break;
+ }
+ printf ("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
+ printf ("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
+ printf ("Register R%x\n", (state & 0x3E) >> 5);
+ hang ();
+}
+
+#ifdef CONFIG_SYS_USR_EXCEP
+void _exception_handler (void)
+{
+ puts ("User vector_exception\n");
+ hang ();
+}
+#endif
diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
new file mode 100644
index 000000000..a6021c99c
--- /dev/null
+++ b/arch/microblaze/cpu/interrupts.c
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/microblaze_intc.h>
+#include <asm/asm.h>
+
+#undef DEBUG_INT
+
+extern void microblaze_disable_interrupts (void);
+extern void microblaze_enable_interrupts (void);
+
+void enable_interrupts (void)
+{
+ MSRSET(0x2);
+}
+
+int disable_interrupts (void)
+{
+ MSRCLR(0x2);
+ return 0;
+}
+
+#ifdef CONFIG_SYS_INTC_0
+#ifdef CONFIG_SYS_TIMER_0
+extern void timer_init (void);
+#endif
+#ifdef CONFIG_SYS_FSL_2
+extern void fsl_init2 (void);
+#endif
+
+
+static struct irq_action vecs[CONFIG_SYS_INTC_0_NUM];
+
+/* mapping structure to interrupt controller */
+microblaze_intc_t *intc = (microblaze_intc_t *) (CONFIG_SYS_INTC_0_ADDR);
+
+/* default handler */
+void def_hdlr (void)
+{
+ puts ("def_hdlr\n");
+}
+
+void enable_one_interrupt (int irq)
+{
+ int mask;
+ int offset = 1;
+ offset <<= irq;
+ mask = intc->ier;
+ intc->ier = (mask | offset);
+#ifdef DEBUG_INT
+ printf ("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
+ intc->ier);
+ printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
+#endif
+}
+
+void disable_one_interrupt (int irq)
+{
+ int mask;
+ int offset = 1;
+ offset <<= irq;
+ mask = intc->ier;
+ intc->ier = (mask & ~offset);
+#ifdef DEBUG_INT
+ printf ("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
+ intc->ier);
+ printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
+#endif
+}
+
+/* adding new handler for interrupt */
+void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
+{
+ struct irq_action *act;
+ /* irq out of range */
+ if ((irq < 0) || (irq > CONFIG_SYS_INTC_0_NUM)) {
+ puts ("IRQ out of range\n");
+ return;
+ }
+ act = &vecs[irq];
+ if (hdlr) { /* enable */
+ act->handler = hdlr;
+ act->arg = arg;
+ act->count = 0;
+ enable_one_interrupt (irq);
+ } else { /* disable */
+ act->handler = (interrupt_handler_t *) def_hdlr;
+ act->arg = (void *)irq;
+ disable_one_interrupt (irq);
+ }
+}
+
+/* initialization interrupt controller - hardware */
+void intc_init (void)
+{
+ intc->mer = 0;
+ intc->ier = 0;
+ intc->iar = 0xFFFFFFFF;
+ /* XIntc_Start - hw_interrupt enable and all interrupt enable */
+ intc->mer = 0x3;
+#ifdef DEBUG_INT
+ printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
+#endif
+}
+
+int interrupts_init (void)
+{
+ int i;
+ /* initialize irq list */
+ for (i = 0; i < CONFIG_SYS_INTC_0_NUM; i++) {
+ vecs[i].handler = (interrupt_handler_t *) def_hdlr;
+ vecs[i].arg = (void *)i;
+ vecs[i].count = 0;
+ }
+ /* initialize intc controller */
+ intc_init ();
+#ifdef CONFIG_SYS_TIMER_0
+ timer_init ();
+#endif
+#ifdef CONFIG_SYS_FSL_2
+ fsl_init2 ();
+#endif
+ enable_interrupts ();
+ return 0;
+}
+
+void interrupt_handler (void)
+{
+ int irqs = (intc->isr & intc->ier); /* find active interrupt */
+ int i = 1;
+#ifdef DEBUG_INT
+ int value;
+ printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
+ R14(value);
+ printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
+#endif
+ struct irq_action *act = vecs;
+ while (irqs) {
+ if (irqs & 1) {
+#ifdef DEBUG_INT
+ printf
+ ("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
+ act->handler, act->count, act->arg);
+#endif
+ act->handler (act->arg);
+ act->count++;
+ intc->iar = i;
+ return;
+ }
+ irqs >>= 1;
+ act++;
+ i <<= 1;
+ }
+
+#ifdef DEBUG_INT
+ printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
+ intc->ier, intc->iar, intc->mer);
+ R14(value);
+ printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
+#endif
+}
+#endif
+
+#if defined(CONFIG_CMD_IRQ)
+#ifdef CONFIG_SYS_INTC_0
+int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ int i;
+ struct irq_action *act = vecs;
+
+ puts ("\nInterrupt-Information:\n\n"
+ "Nr Routine Arg Count\n"
+ "-----------------------------\n");
+
+ for (i = 0; i < CONFIG_SYS_INTC_0_NUM; i++) {
+ if (act->handler != (interrupt_handler_t*) def_hdlr) {
+ printf ("%02d %08x %08x %d\n", i,
+ (int)act->handler, (int)act->arg, act->count);
+ }
+ act++;
+ }
+ puts ("\n");
+ return (0);
+}
+#else
+int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+ puts ("Undefined interrupt controller\n");
+}
+#endif
+#endif
diff --git a/arch/microblaze/cpu/irq.S b/arch/microblaze/cpu/irq.S
new file mode 100644
index 000000000..e1fc19046
--- /dev/null
+++ b/arch/microblaze/cpu/irq.S
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+ .text
+ .global _interrupt_handler
+_interrupt_handler:
+ addi r1, r1, -4
+ swi r2, r1, 0
+ addi r1, r1, -4
+ swi r3, r1, 0
+ addi r1, r1, -4
+ swi r4, r1, 0
+ addi r1, r1, -4
+ swi r5, r1, 0
+ addi r1, r1, -4
+ swi r6, r1, 0
+ addi r1, r1, -4
+ swi r7, r1, 0
+ addi r1, r1, -4
+ swi r8, r1, 0
+ addi r1, r1, -4
+ swi r9, r1, 0
+ addi r1, r1, -4
+ swi r10, r1, 0
+ addi r1, r1, -4
+ swi r11, r1, 0
+ addi r1, r1, -4
+ swi r12, r1, 0
+ addi r1, r1, -4
+ swi r13, r1, 0
+ addi r1, r1, -4
+ swi r14, r1, 0
+ addi r1, r1, -4
+ swi r15, r1, 0
+ addi r1, r1, -4
+ swi r16, r1, 0
+ addi r1, r1, -4
+ swi r17, r1, 0
+ addi r1, r1, -4
+ swi r18, r1, 0
+ addi r1, r1, -4
+ swi r19, r1, 0
+ addi r1, r1, -4
+ swi r20, r1, 0
+ addi r1, r1, -4
+ swi r21, r1, 0
+ addi r1, r1, -4
+ swi r22, r1, 0
+ addi r1, r1, -4
+ swi r23, r1, 0
+ addi r1, r1, -4
+ swi r24, r1, 0
+ addi r1, r1, -4
+ swi r25, r1, 0
+ addi r1, r1, -4
+ swi r26, r1, 0
+ addi r1, r1, -4
+ swi r27, r1, 0
+ addi r1, r1, -4
+ swi r28, r1, 0
+ addi r1, r1, -4
+ swi r29, r1, 0
+ addi r1, r1, -4
+ swi r30, r1, 0
+ addi r1, r1, -4
+ swi r31, r1, 0
+ brlid r15, interrupt_handler
+ nop
+ nop
+ lwi r31, r1, 0
+ addi r1, r1, 4
+ lwi r30, r1, 0
+ addi r1, r1, 4
+ lwi r29, r1, 0
+ addi r1, r1, 4
+ lwi r28, r1, 0
+ addi r1, r1, 4
+ lwi r27, r1, 0
+ addi r1, r1, 4
+ lwi r26, r1, 0
+ addi r1, r1, 4
+ lwi r25, r1, 0
+ addi r1, r1, 4
+ lwi r24, r1, 0
+ addi r1, r1, 4
+ lwi r23, r1, 0
+ addi r1, r1, 4
+ lwi r22, r1, 0
+ addi r1, r1, 4
+ lwi r21, r1, 0
+ addi r1, r1, 4
+ lwi r20, r1, 0
+ addi r1, r1, 4
+ lwi r19, r1, 0
+ addi r1, r1, 4
+ lwi r18, r1, 0
+ addi r1, r1, 4
+ lwi r17, r1, 0
+ addi r1, r1, 4
+ lwi r16, r1, 0
+ addi r1, r1, 4
+ lwi r15, r1, 0
+ addi r1, r1, 4
+ lwi r14, r1, 0
+ addi r1, r1, 4
+ lwi r13, r1, 0
+ addi r1, r1, 4
+ lwi r12, r1, 0
+ addi r1, r1, 4
+ lwi r11, r1, 0
+ addi r1, r1, 4
+ lwi r10, r1, 0
+ addi r1, r1, 4
+ lwi r9, r1, 0
+ addi r1, r1, 4
+ lwi r8, r1, 0
+ addi r1, r1, 4
+ lwi r7, r1, 0
+ addi r1, r1, 4
+ lwi r6, r1, 0
+ addi r1, r1, 4
+ lwi r5, r1, 0
+ addi r1, r1, 4
+ lwi r4, r1, 0
+ addi r1, r1, 4
+ lwi r3, r1, 0
+ addi r1, r1, 4
+ lwi r2, r1, 0
+ addi r1, r1, 4
+
+ /* enable_interrupt */
+#ifdef XILINX_USE_MSR_INSTR
+ msrset r0, 2
+#else
+ /* FIXME unstable in stressed mode - two irqs */
+ nop
+ addi r1, r1, -4
+ swi r12, r1, 0
+ mfs r12, rmsr
+ ori r12, r12, 2
+ mts rmsr, r12
+ lwi r12, r1, 0
+ addi r1, r1, 4
+ nop
+#endif
+ bra r14
+ nop
+ nop
+ .size _interrupt_handler,.-_interrupt_handler
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
new file mode 100644
index 000000000..2e9a08dc5
--- /dev/null
+++ b/arch/microblaze/cpu/start.S
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ * Yasushi SHOJI <yashi@atmark-techno.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+ .text
+ .global _start
+_start:
+ mts rmsr, r0 /* disable cache */
+ addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
+ addi r1, r1, -4 /* Decrement SP to top of memory */
+ /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
+ addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
+ swi r6, r0, 0x0 /* reset address */
+ swi r6, r0, 0x8 /* user vector exception */
+ swi r6, r0, 0x10 /* interrupt */
+ swi r6, r0, 0x20 /* hardware exception */
+
+ addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
+ swi r6, r0, 0x4 /* reset address */
+ swi r6, r0, 0xC /* user vector exception */
+ swi r6, r0, 0x14 /* interrupt */
+ swi r6, r0, 0x24 /* hardware exception */
+
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ /* reset address */
+ addik r6, r0, CONFIG_SYS_RESET_ADDRESS
+ sw r6, r1, r0
+ lhu r7, r1, r0
+ shi r7, r0, 0x2
+ shi r6, r0, 0x6
+/*
+ * Copy U-Boot code to TEXT_BASE
+ * solve problem with sbrk_base
+ */
+#if (CONFIG_SYS_RESET_ADDRESS != TEXT_BASE)
+ addi r4, r0, __end
+ addi r5, r0, __text_start
+ rsub r4, r5, r4 /* size = __end - __text_start */
+ addi r6, r0, CONFIG_SYS_RESET_ADDRESS /* source address */
+ addi r7, r0, 0 /* counter */
+4:
+ lw r8, r6, r7
+ sw r8, r5, r7
+ addi r7, r7, 0x4
+ cmp r8, r4, r7
+ blti r8, 4b
+#endif
+#endif
+
+#ifdef CONFIG_SYS_USR_EXCEP
+ /* user_vector_exception */
+ addik r6, r0, _exception_handler
+ sw r6, r1, r0
+ lhu r7, r1, r0
+ shi r7, r0, 0xa
+ shi r6, r0, 0xe
+#endif
+
+#ifdef CONFIG_SYS_INTC_0
+ /* interrupt_handler */
+ addik r6, r0, _interrupt_handler
+ sw r6, r1, r0
+ lhu r7, r1, r0
+ shi r7, r0, 0x12
+ shi r6, r0, 0x16
+#endif
+
+ /* hardware exception */
+ addik r6, r0, _hw_exception_handler
+ sw r6, r1, r0
+ lhu r7, r1, r0
+ shi r7, r0, 0x22
+ shi r6, r0, 0x26
+
+ /* enable instruction and data cache */
+ mfs r12, rmsr
+ ori r12, r12, 0xa0
+ mts rmsr, r12
+
+clear_bss:
+ /* clear BSS segments */
+ addi r5, r0, __bss_start
+ addi r4, r0, __bss_end
+ cmp r6, r5, r4
+ beqi r6, 3f
+2:
+ swi r0, r5, 0 /* write zero to loc */
+ addi r5, r5, 4 /* increment to next loc */
+ cmp r6, r5, r4 /* check if we have reach the end */
+ bnei r6, 2b
+3: /* jumping to board_init */
+ brai board_init
+1: bri 1b
+
+/*
+ * Read 16bit little endian
+ */
+ .text
+ .global in16
+ .ent in16
+ .align 2
+in16: lhu r3, r0, r5
+ bslli r4, r3, 8
+ bsrli r3, r3, 8
+ andi r4, r4, 0xffff
+ or r3, r3, r4
+ rtsd r15, 8
+ sext16 r3, r3
+ .end in16
+
+/*
+ * Write 16bit little endian
+ * first parameter(r5) - address, second(r6) - short value
+ */
+ .text
+ .global out16
+ .ent out16
+ .align 2
+out16: bslli r3, r6, 8
+ bsrli r6, r6, 8
+ andi r3, r3, 0xffff
+ or r3, r3, r6
+ sh r3, r0, r5
+ rtsd r15, 8
+ or r0, r0, r0
+ .end out16
diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c
new file mode 100644
index 000000000..a91eabc64
--- /dev/null
+++ b/arch/microblaze/cpu/timer.c
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/microblaze_timer.h>
+#include <asm/microblaze_intc.h>
+
+volatile int timestamp = 0;
+
+void reset_timer (void)
+{
+ timestamp = 0;
+}
+
+#ifdef CONFIG_SYS_TIMER_0
+ulong get_timer (ulong base)
+{
+ return (timestamp - base);
+}
+#else
+ulong get_timer (ulong base)
+{
+ return (timestamp++ - base);
+}
+#endif
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+#ifdef CONFIG_SYS_INTC_0
+#ifdef CONFIG_SYS_TIMER_0
+microblaze_timer_t *tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR);
+
+void timer_isr (void *arg)
+{
+ timestamp++;
+ tmr->control = tmr->control | TIMER_INTERRUPT;
+}
+
+void timer_init (void)
+{
+ tmr->loadreg = CONFIG_SYS_TIMER_0_PRELOAD;
+ tmr->control = TIMER_INTERRUPT | TIMER_RESET;
+ tmr->control =
+ TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
+ reset_timer ();
+ install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr);
+}
+#endif
+#endif