Merge branch 'master' of git://git.denx.de/u-boot-pxa

4 files changed, 451 insertions, 7 deletions

diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c
index d56c5f099..524a03b62 100644
--- a/arch/arm/cpu/pxa/pxafb.c
+++ b/arch/arm/cpu/pxa/pxafb.c
@@ -112,6 +112,39 @@ vidinfo_t panel_info = {
 	vl_efw:		0,
 };
 #endif /* CONFIG_SHARP_LM8V31 */
+/*----------------------------------------------------------------------*/
+#ifdef CONFIG_VOIPAC_LCD
+
+# define LCD_BPP	LCD_COLOR8
+# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0	0x043008f8
+# define REG_LCCR3	0x0340FF08
+
+vidinfo_t panel_info = {
+	vl_col:		640,
+	vl_row:		480,
+	vl_width:	157,
+	vl_height:	118,
+	vl_clkp:	CONFIG_SYS_HIGH,
+	vl_oep:		CONFIG_SYS_HIGH,
+	vl_hsp:		CONFIG_SYS_HIGH,
+	vl_vsp:		CONFIG_SYS_HIGH,
+	vl_dp:		CONFIG_SYS_HIGH,
+	vl_bpix:	LCD_BPP,
+	vl_lbw:		0,
+	vl_splt:	1,
+	vl_clor:	1,
+	vl_tft:		1,
+	vl_hpw:		32,
+	vl_blw:		144,
+	vl_elw:		32,
+	vl_vpw:		2,
+	vl_bfw:		13,
+	vl_efw:		30,
+};
+#endif /* CONFIG_VOIPAC_LCD */
 
 /*----------------------------------------------------------------------*/
 #ifdef CONFIG_HITACHI_SX14
@@ -147,6 +180,40 @@ vidinfo_t panel_info = {
 #endif /* CONFIG_HITACHI_SX14 */
 
 /*----------------------------------------------------------------------*/
+#ifdef CONFIG_LMS283GF05
+
+# define LCD_BPP	LCD_COLOR8
+//# define LCD_INVERT_COLORS
+
+/* you have to set lccr0 and lccr3 (including pcd) */
+# define REG_LCCR0	0x043008f8
+# define REG_LCCR3	0x03b00009
+
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_width:	240,
+	vl_height:	320,
+	vl_clkp:	CONFIG_SYS_HIGH,
+	vl_oep:		CONFIG_SYS_LOW,
+	vl_hsp:		CONFIG_SYS_LOW,
+	vl_vsp:		CONFIG_SYS_LOW,
+	vl_dp:		CONFIG_SYS_HIGH,
+	vl_bpix:	LCD_BPP,
+	vl_lbw:		0,
+	vl_splt:	1,
+	vl_clor:	1,
+	vl_tft:		1,
+	vl_hpw:		4,
+	vl_blw:		4,
+	vl_elw:		8,
+	vl_vpw:		4,
+	vl_bfw:		4,
+	vl_efw:		8,
+};
+#endif /* CONFIG_LMS283GF05 */
+
+/*----------------------------------------------------------------------*/
 
 #if LCD_BPP == LCD_COLOR8
 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
@@ -292,7 +359,9 @@ static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
 
 	return 0;
 }
-
+#ifdef	CONFIG_CPU_MONAHANS
+static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
+#else
 static void pxafb_setup_gpio (vidinfo_t *vid)
 {
 	u_long lccr0;
@@ -349,6 +418,7 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
 		printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
 	}
 }
+#endif
 
 static void pxafb_enable_controller (vidinfo_t *vid)
 {
@@ -363,7 +433,11 @@ static void pxafb_enable_controller (vidinfo_t *vid)
 	FDADR1 = vid->pxa.fdadr1;
 	LCCR0 |= LCCR0_ENB;
 
+#ifdef	CONFIG_CPU_MONAHANS
+	CKENA |= CKENA_1_LCD;
+#else
 	CKEN |= CKEN16_LCD;
+#endif
 
 	debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
 	debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index e07c8c2e0..8010b0ee1 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -34,6 +34,25 @@
 
 .globl _start
 _start: b	reset
+#ifdef CONFIG_PRELOADER
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+	ldr	pc, _hang
+
+_hang:
+	.word	do_hang
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678
+	.word	0x12345678	/* now 16*4=64 */
+#else
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -49,6 +68,7 @@ _data_abort:		.word data_abort
 _not_used:		.word not_used
 _irq:			.word irq
 _fiq:			.word fiq
+#endif	/* CONFIG_PRELOADER */
 
 	.balignl 16,0xdeadbeef
 
@@ -117,8 +137,10 @@ reset:
 relocate:				/* relocate U-Boot to RAM	    */
 	adr	r0, _start		/* r0 <- current position of code   */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
+#ifndef	CONFIG_PRELOADER
 	cmp	r0, r1			/* don't reloc during debug	    */
 	beq	stack_setup
+#endif
 
 	ldr	r2, _armboot_start
 	ldr	r3, _bss_start
@@ -135,28 +157,37 @@ copy_loop:
 	/* Set up the stack						    */
 stack_setup:
 	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area			    */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo			    */
+#ifdef CONFIG_PRELOADER
+	sub	sp, r0, #128		/* leave 32 words for abort-stack   */
+#else
+	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area		    */
+	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo		    */
 #ifdef CONFIG_USE_IRQ
 	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif /* CONFIG_USE_IRQ */
 	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
 	bic	sp, sp, #7		/* 8-byte alignment for ABI compliance */
+#endif
 
 clear_bss:
 	ldr	r0, _bss_start		/* find start of bss segment	    */
 	ldr	r1, _bss_end		/* stop here			    */
 	mov	r2, #0x00000000		/* clear			    */
 
+#ifndef CONFIG_PRELOADER
 clbss_l:str	r2, [r0]		/* clear loop...		    */
 	add	r0, r0, #4
 	cmp	r0, r1
 	ble	clbss_l
+#endif
 
 	ldr	pc, _start_armboot
 
+#ifdef CONFIG_ONENAND_IPL
+_start_armboot: .word start_oneboot
+#else
 _start_armboot: .word start_armboot
-
+#endif
 
 /****************************************************************************/
 /*									    */
@@ -296,7 +327,7 @@ setspeed_done:
 */
 	mov	pc, lr
 
-
+#ifndef CONFIG_PRELOADER
 /****************************************************************************/
 /*									    */
 /* Interrupt handling							    */
@@ -394,6 +425,7 @@ setspeed_done:
 	.macro get_fiq_stack			@ setup FIQ stack
 	ldr	sp, FIQ_STACK_START
 	.endm
+#endif	/* CONFIG_PRELOADER */
 
 
 /****************************************************************************/
@@ -402,6 +434,12 @@ setspeed_done:
 /*									    */
 /****************************************************************************/
 
+#ifdef CONFIG_PRELOADER
+	.align	5
+do_hang:
+	ldr	sp, _TEXT_BASE			/* use 32 words abort stack */
+	bl	hang				/* hang and never return */
+#else	/* !CONFIG_PRELOADER */
 	.align	5
 undefined_instruction:
 	get_bad_stack
@@ -461,7 +499,7 @@ fiq:
 	get_bad_stack
 	bad_save_user_regs
 	bl	do_fiq
-
+#endif	/* CONFIG_PRELOADER */
 #endif /* CONFIG_USE_IRQ */
 
 /****************************************************************************/
diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h
new file mode 100644
index 000000000..035a57e0a
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/macro.h
@@ -0,0 +1,324 @@
+/*
+ * arch/arm/include/asm/arch-pxa/macro.h
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_PXA_MACRO_H__
+#define __ASM_ARCH_PXA_MACRO_H__
+#ifdef __ASSEMBLY__
+
+#include <asm/macro.h>
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * This macro performs a 32bit write to a memory location and makes sure the
+ * write operation really happened by performing a read back.
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro	write32rb addr, data
+	ldr	r4, =\addr
+	ldr	r5, =\data
+	str	r5, [r4]
+	ldr	r5, [r4]
+.endm
+
+/*
+ * This macro waits according to OSCR incrementation
+ *
+ * Clobbered regs: r4, r5, r6
+ */
+.macro	pxa_wait_ticks ticks
+	ldr	r4, =OSCR
+	mov	r5, #0
+	str	r5, [r4]
+	ldr	r5, =\ticks
+1:
+	ldr	r6, [r4]
+	cmp	r5, r6
+	bgt	1b
+.endm
+
+/*
+ * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro	pxa_gpio_setup
+	write32	GPSR0, CONFIG_SYS_GPSR0_VAL
+	write32	GPSR1, CONFIG_SYS_GPSR1_VAL
+	write32	GPSR2, CONFIG_SYS_GPSR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	write32	GPSR3, CONFIG_SYS_GPSR3_VAL
+#endif
+
+	write32	GPCR0, CONFIG_SYS_GPCR0_VAL
+	write32	GPCR1, CONFIG_SYS_GPCR1_VAL
+	write32	GPCR2, CONFIG_SYS_GPCR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	write32	GPCR3, CONFIG_SYS_GPCR3_VAL
+#endif
+
+	write32	GPDR0, CONFIG_SYS_GPDR0_VAL
+	write32	GPDR1, CONFIG_SYS_GPDR1_VAL
+	write32	GPDR2, CONFIG_SYS_GPDR2_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	write32	GPDR3, CONFIG_SYS_GPDR3_VAL
+#endif
+
+	write32	GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
+	write32	GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
+	write32	GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
+	write32	GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
+	write32	GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
+	write32	GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	write32	GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
+	write32	GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
+#endif
+
+	write32	PSSR, CONFIG_SYS_PSSR_VAL
+.endm
+
+/*
+ * This macro sets up the Memory controller of the PXA2xx CPU
+ *
+ * Clobbered regs: r3, r4, r5
+ */
+.macro	pxa_mem_setup
+	/* This comes handy when setting MDREFR */
+	ldr	r3, =MEMC_BASE
+
+	/*
+	 * 1) Initialize Asynchronous static memory controller
+	 */
+
+	/* MSC0: nCS(0,1) */
+	write32rb	(MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
+	/* MSC1: nCS(2,3) */
+	write32rb	(MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
+	/* MSC2: nCS(4,5) */
+	write32rb	(MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
+
+	/*
+	 * 2) Initialize Card Interface
+	 */
+
+	/* MECR: Memory Expansion Card Register */
+	write32rb	(MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
+	/* MCMEM0: Card Interface slot 0 timing */
+	write32rb	(MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
+	/* MCMEM1: Card Interface slot 1 timing */
+	write32rb	(MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
+	write32rb	(MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
+	write32rb	(MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
+	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
+	write32rb	(MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
+	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
+	write32rb	(MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
+
+	/*
+	 * 3) Configure Fly-By DMA register
+	 */
+
+	write32rb	(MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
+
+	/*
+	 * 4) Initialize Timing for Sync Memory (SDCLK0)
+	 */
+
+	/*
+	 * Before accessing MDREFR we need a valid DRI field, so we set
+	 * this to power on defaults + DRI field.
+	 */
+	ldr	r5, [r3, #MDREFR_OFFSET]
+	bic	r5, r5, #0x0ff
+	bic	r5, r5, #0xf00	/* MDREFR user config with zeroed DRI */
+
+	ldr	r4, =CONFIG_SYS_MDREFR_VAL
+	mov	r6, r4
+	lsl	r4, #20
+	lsr	r4, #20		/* Get a valid DRI field */
+
+	orr	r5, r5, r4	/* MDREFR user config with correct DRI */
+
+	orr	r5, #MDREFR_K0RUN
+	orr	r5, #MDREFR_SLFRSH
+	bic	r5, #MDREFR_APD
+	bic	r5, #MDREFR_E1PIN
+
+	str	r5, [r3, #MDREFR_OFFSET]
+	ldr	r4, [r3, #MDREFR_OFFSET]
+
+	/*
+	 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
+	 */
+
+	/* Initialize SXCNFG register. Assert the enable bits.
+	 *
+	 * Write SXMRS to cause an MRS command to all enabled banks of
+	 * synchronous static memory. Note that SXLCR need not be written
+	 * at this time.
+	 */
+	write32rb	(MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
+
+	/*
+	 * 6) Initialize SDRAM
+	 */
+
+	bic	r6, #MDREFR_SLFRSH
+	str	r6, [r3, #MDREFR_OFFSET]
+	ldr	r4, [r3, #MDREFR_OFFSET]
+
+	orr	r6, #MDREFR_E1PIN
+	str	r6, [r3, #MDREFR_OFFSET]
+	ldr	r4, [r3, #MDREFR_OFFSET]
+
+	/*
+	 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
+	 *    but not enable each SDRAM partition pair.
+	 */
+
+	/* Fetch platform value of MDCNFG */
+	ldr	r4, =CONFIG_SYS_MDCNFG_VAL
+	/* Disable all sdram banks */
+	bic	r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
+	bic	r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
+	/* Write initial value of MDCNFG, w/o enabling sdram banks */
+	str	r4, [r3, #MDCNFG_OFFSET]
+	ldr	r4, [r3, #MDCNFG_OFFSET]
+
+	/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
+	pxa_wait_ticks	0x300
+
+	/*
+	 * 8) Trigger a number (usually 8) refresh cycles by attempting
+	 *    non-burst read or write accesses to disabled SDRAM, as commonly
+	 *    specified in the power up sequence documented in SDRAM data
+	 *    sheets. The address(es) used for this purpose must not be
+	 *    cacheable.
+	 */
+
+	ldr	r4, =CONFIG_SYS_DRAM_BASE
+.rept 9
+	str	r5, [r4]
+.endr
+
+	/*
+	 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
+	 */
+
+	ldr	r5, =CONFIG_SYS_MDCNFG_VAL
+	ldr	r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
+	and	r5, r5, r4
+	ldr     r4, [r3, #MDCNFG_OFFSET]
+	orr	r4, r4, r5
+	str     r4, [r3, #MDCNFG_OFFSET]
+	ldr     r4, [r3, #MDCNFG_OFFSET]
+
+	/*
+	 * 10) Write MDMRS.
+	 */
+
+	ldr     r4, =CONFIG_SYS_MDMRS_VAL
+	str     r4, [r3, #MDMRS_OFFSET]
+	ldr     r4, [r3, #MDMRS_OFFSET]
+
+	/*
+	 * 11) Enable APD
+	 */
+
+	ldr	r4, [r3, #MDREFR_OFFSET]
+	and	r6, r6, #MDREFR_APD
+	orr	r4, r4, r6
+	str	r4, [r3, #MDREFR_OFFSET]
+	ldr	r4, [r3, #MDREFR_OFFSET]
+.endm
+
+/*
+ * This macro tests if the CPU woke up from sleep and eventually resumes
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro	pxa_wakeup
+	ldr	r4, =RCSR
+	ldr	r5, [r4]
+	and	r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+	str	r5, [r4]
+	teq	r5, #RCSR_SMR
+
+	bne	pxa_wakeup_exit
+
+	ldr	r4, =PSSR
+	mov	r5, #PSSR_PH
+	str	r5, [r4]
+
+	ldr	r4, =PSPR
+	ldr	pc, [r4]
+pxa_wakeup_exit:
+.endm
+
+/*
+ * This macro disables all interupts on PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro	pxa_intr_setup
+	write32	ICLR, 0
+	write32	ICMR, 0
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+	write32	ICLR2, 0
+	write32	ICMR2, 0
+#endif
+.endm
+
+/*
+ * This macro configures clock on PXA2xx/PXA3xx CPU
+ *
+ * Clobbered regs: r4, r5
+ */
+.macro	pxa_clock_setup
+	/* Disable the peripheral clocks, and set the core clock frequency */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration */
+	write32	CKEN, CONFIG_SYS_CKEN
+
+	/* Write CCCR */
+	write32	CCCR, CONFIG_SYS_CCCR
+
+#ifdef CONFIG_RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager */
+	write32	OSCC, #OSCC_OON
+	ldr	r4, =OSCC
+
+	/* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
+2:
+	ldr	r5, [r4]
+	ands	r5, r5, #1
+	beq	2b
+#endif
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_PXA_MACRO_H__ */
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index cd7b7f946..d442fb065 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -1132,10 +1132,18 @@ typedef void		(*ExcpHndlr) (void) ;
 #define PWM_PWDUTY0	__REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
 #define PWM_PERVAL0	__REG(0x40B00008)  /* PWM 0 Period Control Register */
 
-#define PWM_CTRL1	__REG(0x40C00000)  /* PWM 1Control Register */
+#define PWM_CTRL1	__REG(0x40C00000)  /* PWM 1 Control Register */
 #define PWM_PWDUTY1	__REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
 #define PWM_PERVAL1	__REG(0x40C00008)  /* PWM 1 Period Control Register */
 
+#define PWM_CTRL2	__REG(0x40B00010)  /* PWM 2 Control Register */
+#define PWM_PWDUTY2	__REG(0x40B00014)  /* PWM 2 Duty Cycle Register */
+#define PWM_PERVAL2	__REG(0x40B00018)  /* PWM 2 Period Control Register */
+
+#define PWM_CTRL3	__REG(0x40C00010)  /* PWM 3 Control Register */
+#define PWM_PWDUTY3	__REG(0x40C00014)  /* PWM 3 Duty Cycle Register */
+#define PWM_PERVAL3	__REG(0x40C00018)  /* PWM 3 Period Control Register */
+
 /*
  * Interrupt Controller
  */