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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2012-09-27 10:21:22 +0000
committerTom Rini <trini@ti.com>2012-10-15 11:54:10 -0700
commit248cdf0b5270651ca5eefb1aff4a338df6a1ca25 (patch)
treec87a72170aa90295c975b73f9c71eed0af83f7af /arch/arm/include/asm
parent1f5e4ee0b9e06a129a6a1b117d77c77189c18542 (diff)
downloadu-boot-linaro-stable-248cdf0b5270651ca5eefb1aff4a338df6a1ca25.tar.gz
mx5: Fix clock gate values
The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one of these bits like what was done is wrong and can lead to unpredictable behavior depending on the original value of these bit-fields. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-mx5/crm_regs.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index d5eb30338..3b0ed64fc 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -285,6 +285,9 @@ struct mxc_ccm_reg {
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
+#define MXC_CCM_CCGR_CG_OFF 0x0
+#define MXC_CCM_CCGR_CG_RUN_ON 0x1
+#define MXC_CCM_CCGR_CG_ON 0x3
#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0
#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0)