diff options
| author | Marek Vasut <marek.vasut@gmail.com> | 2011-09-23 11:43:47 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-30 22:01:05 +0200 |
| commit | bf2eaf5112af4e550420c38b60a15f66a3ff0880 (patch) | |
| tree | 7a4b3adc5ea8772da8d8a584be5113c348b7f49f /arch/arm/include/asm/arch-mx5/imx-regs.h | |
| parent | 00e11a439729a1a63ec13fea85a4c091c2d0376c (diff) | |
MX5: Modify the PLL decoding algorithm
The PLL decoding algorithm didn't take into account many configuration bits.
Adjust it according to Linux kernel. Also, add PLL4 for MX53.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Hui <jason.hui@linaro.org>
Tested-by: Jason Liu <Jason.hui@linaro.org>
Diffstat (limited to 'arch/arm/include/asm/arch-mx5/imx-regs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/imx-regs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 098c30090..d069209b5 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -100,6 +100,9 @@ #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#ifdef CONFIG_MX53 +#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) +#endif #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) |