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/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
* above copyright notice, this list of conditions and
* the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*/
#ifndef __CACHE_GEOM_H__
#define __CACHE_GEOM_H__
#include "misc.h"
/* Target cpu cache relative to host cpu cache size */
#define TCSZ_EQUAL 0x0
#define TCSZ_SMALL 0x1
#define TCSZ_BIG 0x2
/* Cache Instruction not Data bit, CSSELR[0] */
#define CIND_DATA 0x0 /* Data cache */
#define CIND_UNIF CIND_DATA /* Unified cache */
#define CIND_INST 0x1 /* Instruction cache */
/* A7 L1 instruction cache CCSIDR value */
#define CACHE_A7_L1_INST_CCSIDR 0x203FE009
#define get_setway_reg(a, b , c, d, e) ((a << __clz(b)) | (c << (d + 4)) | (e << 1))
#define get_cache_type(clidr, lvl) ((clidr >> (lvl * 0x3)) & 0x7)
#define get_cache_level(reg) ((reg >> 1) & 0x7)
#define get_cache_ind(reg) (reg & 0x1)
#define get_cache_linesz(cg, lvl) (cg->ccsidr[lvl][CIND_DATA] & 0x7)
#define get_cache_assoc(cg, lvl) ((cg->ccsidr[lvl][CIND_DATA] >> 3) & 0x3ff)
#define get_cache_numsets(cg, lvl) ((cg->ccsidr[lvl][CIND_DATA] >> 13) & 0x7fff)
/*
* Data structure that stores the foreseeable differences
* between the host and target caches at each implemented
* cache level.
* Absolute cache line numbers are calculated relative to
* the cache line size of the smaller cache to get the
* maximum granularity.
*/
typedef struct cache_diff {
/* Stores whether target cache is =,<,> host cache */
unsigned csize_diff;
/*
* Stores factor by which target cache line
* has to be multiplied to get absolute line
* no.
*/
unsigned tcline_factor;
/*
* Stores factor by which absolute cache line
* no. has to be divided to get host cache line
* no.
*/
unsigned hcline_factor;
/* Max absolute target cpu cache line number */
unsigned tnumabs_clines;
/* Max absolute host cpu cache line number */
unsigned hnumabs_clines;
} cache_diff;
/*
* Data structure that defines the cache topology of a cpu
*/
typedef struct cache_geom {
unsigned clidr;
/*
* One for each cpu to store the cache level
* the OS thinks its operating on.
*/
unsigned csselr;
/* One for each cache level and variant */
unsigned ccsidr[MAX_CACHE_LEVELS][MAX_CACHE_VARIANTS];
} cache_geometry;
/*
* Data structure to hold cache virtualisation statistics.
* Reset for each switchover.
*/
typedef struct cache_stats {
/* Number of cm ops which did not cover the whole cache */
unsigned part_cmop_cnt;
/* Number of cm ops which spanned the entire cache */
unsigned cmpl_cmop_cnt;
} cache_stats;
extern unsigned map_cache_geometries(cache_geometry *, cache_geometry *,
cache_diff *);
extern void find_cache_geometry(cache_geometry *);
extern void find_cache_diff(cache_geometry *, cache_geometry *, cache_diff *);
extern void handle_cm_op(unsigned, void (*)(unsigned), cache_geometry *,
cache_geometry *, cache_diff *);
//extern void stat_init_host_cache_geometry(cache_geometry *);
#endif /* __CACHE_GEOM_H__ */
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