diff options
Diffstat (limited to 'acsr/v7.s')
| -rw-r--r-- | acsr/v7.s | 148 |
1 files changed, 74 insertions, 74 deletions
@@ -1,24 +1,24 @@ ; ; Copyright (c) 2012, ARM Limited. All rights reserved. - ; - ; Redistribution and use in source and binary forms, with - ; or without modification, are permitted provided that the - ; following conditions are met: - ; - ; Redistributions of source code must retain the above - ; copyright notice, this list of conditions and the - ; following disclaimer. - ; - ; Redistributions in binary form must reproduce the - ; above copyright notice, this list of conditions and - ; the following disclaimer in the documentation - ; and/or other materials provided with the distribution. - ; - ; Neither the name of ARM nor the names of its - ; contributors may be used to endorse or promote products - ; derived from this software without specific prior written - ; permission. - ; + ; + ; Redistribution and use in source and binary forms, with + ; or without modification, are permitted provided that the + ; following conditions are met: + ; + ; Redistributions of source code must retain the above + ; copyright notice, this list of conditions and the + ; following disclaimer. + ; + ; Redistributions in binary form must reproduce the + ; above copyright notice, this list of conditions and + ; the following disclaimer in the documentation + ; and/or other materials provided with the distribution. + ; + ; Neither the name of ARM nor the names of its + ; contributors may be used to endorse or promote products + ; derived from this software without specific prior written + ; permission. + ; EXPORT save_performance_monitors EXPORT restore_performance_monitors @@ -45,7 +45,7 @@ EXPORT restore_generic_timer EXPORT save_fault_status - EXPORT restore_fault_status + EXPORT restore_fault_status AREA APPF, CODE @@ -62,7 +62,7 @@ MODE_HYP EQU 0x1A TTBCR_EAE EQU (1<<31) ; Are we using LPAE? -PFR0_THUMB_EE_SUPPORT EQU (1<<12) +PFR0_THUMB_EE_SUPPORT EQU (1<<12) save_performance_monitors FUNCTION @@ -73,14 +73,14 @@ save_performance_monitors FUNCTION bic r1,r8,#1 mcr p15,0,r1,c9,c12,0 ; disable counter updates from here isb ; 0b0 => PMCR<0> - mrc p15,0,r9,c9,c12,5 ; PMon: Event Counter Selection Register + mrc p15,0,r9,c9,c12,5 ; PMon: Event Counter Selection Register mrc p15,0,r10,c9,c12,1 ; PMon: Count Enable Set Reg stm r0!, {r8-r10} - mrc p15,0,r8,c9,c12,2 ; PMon: Count Enable Clear Register + mrc p15,0,r8,c9,c12,2 ; PMon: Count Enable Clear Register mrc p15,0,r9,c9,c13,0 ; PMon: Cycle Counter Register mrc p15,0,r10,c9,c12,3 ; PMon: Overflow flag Status Register stm r0!, {r8-r10} - mrc p15,0,r8,c9,c14,1 ; PMon: Interrupt Enable Set Registern + mrc p15,0,r8,c9,c14,1 ; PMon: Interrupt Enable Set Registern mrc p15,0,r9,c9,c14,2 ; PMon: Interrupt Enable Clear Register stm r0!, {r8-r9} mrc p15,0,r8,c9,c12,0 ; Read PMon Control Register @@ -120,15 +120,15 @@ restore_performance_monitors FUNCTION tst r12, r12 beq %f20 - add r1,r0,#32 ; r1 now points to the 1st saved event counter + add r1,r0,#32 ; r1 now points to the 1st saved event counter ;; Restore counters mov r6,#0 10 mcr p15,0,r6,c9,c12,5 ; PMon: select CounterN isb - ldm r1!, {r3,r4} ; Read saved data + ldm r1!, {r3,r4} ; Read saved data mcr p15,0,r3,c9,c13,1 ; PMon: restore Event Type Register mcr p15,0,r4,c9,c13,2 ; PMon: restore Event Counter Register - add r6,r6,#1 ; increment index + add r6,r6,#1 ; increment index cmps r6,r12 bne %b10 @@ -154,13 +154,13 @@ restore_performance_monitors FUNCTION ;; Restore left regs but PMCR add r1,r0,#4 ; r1 now points to the PMSELR ldm r1!,{r3,r4} - mcr p15,0,r3,c9,c12,5 ; PMon: Event Counter Selection Reg + mcr p15,0,r3,c9,c12,5 ; PMon: Event Counter Selection Reg mcr p15,0,r4,c9,c12,1 ; PMon: Count Enable Set Reg ldm r1!, {r3,r4} mcr p15,0,r4,c9,c13,0 ; PMon: Cycle Counter Register ldm r1!,{r3,r4} mcr p15,0,r3,c9,c14,2 ; PMon: Interrupt Enable Clear Reg - mcr p15,0,r4,c9,c14,1 ; PMon: Interrupt Enable Set Reg + mcr p15,0,r4,c9,c14,1 ; PMon: Interrupt Enable Set Reg ldr r3,[r1] isb ldr r0,[r0] @@ -180,20 +180,20 @@ save_banked_registers FUNCTION str sp,[r0], #4 ; save the User SP str lr,[r0], #4 ; save the User LR cps #MODE_ABT ; switch to Abort mode - str sp,[r0], #4 ; save the current SP - mrs r3,SPSR + str sp,[r0], #4 ; save the current SP + mrs r3,SPSR stm r0!,{r3,lr} ; save the current SPSR, LR cps #MODE_UND ; switch to Undefined mode str sp,[r0], #4 ; save the current SP - mrs r3,SPSR + mrs r3,SPSR stm r0!,{r3,lr} ; save the current SPSR, LR cps #MODE_IRQ ; switch to IRQ mode str sp,[r0], #4 ; save the current SP - mrs r3,SPSR + mrs r3,SPSR stm r0!,{r3,lr} ; save the current SPSR, LR cps #MODE_FIQ ; switch to FIQ mode str SP,[r0], #4 ; save the current SP - mrs r3,SPSR + mrs r3,SPSR stm r0!,{r8-r12,lr} ; save the current SPSR,r8-r12,LR msr CPSR_cxsf, r2 ; switch back to original mode bx lr @@ -243,23 +243,23 @@ restore_banked_registers FUNCTION cmp r3, #MODE_HYP ; instructions to restore the banked registers beq rest_in_hyp ; without changing the mode - cps #MODE_SYS ; switch to System mode - ldr sp,[r0],#4 ; restore the User SP + cps #MODE_SYS ; switch to System mode + ldr sp,[r0],#4 ; restore the User SP ldr lr,[r0],#4 ; restore the User LR - cps #MODE_ABT ; switch to Abort mode - ldr sp,[r0],#4 ; restore the current SP - ldm r0!,{r3,lr} ; restore the current LR + cps #MODE_ABT ; switch to Abort mode + ldr sp,[r0],#4 ; restore the current SP + ldm r0!,{r3,lr} ; restore the current LR msr SPSR_fsxc,r3 ; restore the current SPSR - cps #MODE_UND ; switch to Undefined mode - ldr sp,[r0],#4 ; restore the current SP - ldm r0!,{r3,lr} ; restore the current LR + cps #MODE_UND ; switch to Undefined mode + ldr sp,[r0],#4 ; restore the current SP + ldm r0!,{r3,lr} ; restore the current LR msr SPSR_fsxc,r3 ; restore the current SPSR - cps #MODE_IRQ ; switch to IRQ mode - ldr sp,[r0],#4 ; restore the current SP - ldm r0!,{r3,lr} ; restore the current LR + cps #MODE_IRQ ; switch to IRQ mode + ldr sp,[r0],#4 ; restore the current SP + ldm r0!,{r3,lr} ; restore the current LR msr SPSR_fsxc,r3 ; restore the current SPSR - cps #MODE_FIQ ; switch to FIQ mode - ldr sp,[r0],#4 ; restore the current SP + cps #MODE_FIQ ; switch to FIQ mode + ldr sp,[r0],#4 ; restore the current SP ldm r0!,{r8-r12,lr} ; restore the current r8-r12,LR msr SPSR_fsxc,r4 ; restore the current SPSR msr CPSR_cxsf, r2 ; switch back to original mode @@ -274,53 +274,53 @@ rest_in_hyp msr SPSR_und, r2 msr LR_und, r3 - ldm r0!, {r1-r3} + ldm r0!, {r1-r3} msr SP_abt, r1 msr SPSR_abt, r2 msr LR_abt, r3 - ldm r0!, {r1-r3} + ldm r0!, {r1-r3} msr SP_svc, r1 msr SPSR_svc, r2 msr LR_svc, r3 - ldm r0!, {r1-r3} + ldm r0!, {r1-r3} msr SP_irq, r1 msr SPSR_irq, r2 msr LR_irq, r3 - + ldm r0!, {r1-r3} msr SP_fiq, r1 msr SPSR_fiq, r2 - msr LR_fiq, r3 + msr LR_fiq, r3 ldm r0!, {r1-r3} msr r8_fiq, r1 msr r9_fiq, r2 - msr r10_fiq, r3 + msr r10_fiq, r3 ldm r0!, {r1-r2} msr r11_fiq, r1 msr r12_fiq, r2 - - bx lr + + bx lr ENDFUNC - + save_cp15 FUNCTION ; CSSELR Cache Size Selection Register mrc p15,2,r3,c0,c0,0 str r3,[r0], #4 - ; IMPLEMENTATION DEFINED - proprietary features: + ; IMPLEMENTATION DEFINED - proprietary features: ; (CP15 register 15, TCM support, lockdown support, etc.) ; NOTE: IMP DEF registers might have save and restore order that relate - ; to other CP15 registers or logical grouping requirements and can + ; to other CP15 registers or logical grouping requirements and can ; therefore occur at any point in this sequence. bx lr ENDFUNC - + restore_cp15 FUNCTION ; CSSELR – Cache Size Selection Register ldr r3,[r0], #4 @@ -328,7 +328,7 @@ restore_cp15 FUNCTION bx lr ENDFUNC - + ; Function called with two arguments: ; r0 contains address to store control registers ; r1 is non-zero if we are Secure @@ -354,16 +354,16 @@ save_control_registers FUNCTION ; The next two registers are only present if ThumbEE is implemented mrc p15, 0, r1, c0, c1, 0 ; Read ID_PFR0 tst r1, #PFR0_THUMB_EE_SUPPORT - mrcne p14,6,r1,c0,c0,0 ; TEECR + mrcne p14,6,r1,c0,c0,0 ; TEECR mrcne p14,6,r2,c1,c0,0 ; TEEHBR stmne r0!, {r1, r2} - + mrc p14,7,r1,c1,c0,0 ; JOSCR mrc p14,7,r2,c2,c0,0 ; JMCR stm r0!, {r1, r2} bx lr ENDFUNC - + ; Function called with two arguments: ; r0 contains address to read control registers @@ -455,7 +455,7 @@ restore_mmu FUNCTION bx lr ENDFUNC - + save_mpu FUNCTION mrc p15, 0, r1, c0, c0, 4 ; Read MPUIR and r1, r1, #0xff00 @@ -475,7 +475,7 @@ save_mpu FUNCTION 20 bx lr ENDFUNC - + restore_mpu FUNCTION mrc p15, 0, r1, c0, c0, 4 ; Read MPUIR and r1, r1, #0xff00 @@ -500,7 +500,7 @@ save_vfp FUNCTION ; FPU state save/restore. ; FPSID,MVFR0 and MVFR1 don't get serialized/saved (Read Only). mrc p15,0,r3,c1,c0,2 ; CPACR allows CP10 and CP11 access - ORR r2,r3,#0xF00000 + ORR r2,r3,#0xF00000 mcr p15,0,r2,c1,c0,2 isb mrc p15,0,r2,c1,c0,2 @@ -509,7 +509,7 @@ save_vfp FUNCTION beq %f0 movs r2, #0 b %f2 - + 0 ; Save configuration registers and enable. vmrs r12,FPEXC str r12,[r0],#4 ; Save the FPEXC @@ -518,7 +518,7 @@ save_vfp FUNCTION vmsr FPEXC,r2 vmrs r2,FPSCR str r2,[r0],#4 ; Save the FPSCR - ; Store the VFP-D16 registers. + ; Store the VFP-D16 registers. vstm r0!, {D0-D15} ; Check for Advanced SIMD/VFP-D32 support vmrs r2,MVFR0 @@ -528,7 +528,7 @@ save_vfp FUNCTION ; Store the Advanced SIMD/VFP-D32 additional registers. vstm r0!, {D16-D31} - ; IMPLEMENTATION DEFINED: save any subarchitecture defined state + ; IMPLEMENTATION DEFINED: save any subarchitecture defined state ; NOTE: Don't change the order of the FPEXC and CPACR restores 1 vmsr FPEXC,r12 ; Restore the original En bit of FPU. @@ -543,12 +543,12 @@ restore_vfp FUNCTION ; serialized (RO). ; Modify CPACR to allow CP10 and CP11 access mrc p15,0,r1,c1,c0,2 - ORR r2,r1,#0x00F00000 + ORR r2,r1,#0x00F00000 mcr p15,0,r2,c1,c0,2 ; Enable FPU access to save/restore the rest of registers. ldr r2,=0x40000000 vmsr FPEXC, r2 - ; Recover FPEXC and FPSCR. These will be restored later. + ; Recover FPEXC and FPSCR. These will be restored later. ldm r0!,{r3,r12} ; Restore the VFP-D16 registers. vldm r0!, {D0-D15} @@ -561,12 +561,12 @@ restore_vfp FUNCTION ; Store the Advanced SIMD/VFP-D32 additional registers. vldm r0!, {D16-D31} - ; IMPLEMENTATION DEFINED: restore any subarchitecture defined state + ; IMPLEMENTATION DEFINED: restore any subarchitecture defined state 0 ; Restore configuration registers and enable. ; Restore FPSCR _before_ FPEXC since FPEXC could disable FPU ; and make setting FPSCR unpredictable. - vmsr FPSCR,r12 + vmsr FPSCR,r12 vmsr FPEXC,r3 ; Restore FPEXC after FPSCR ; Restore CPACR mcr p15,0,r1,c1,c0,2 @@ -577,7 +577,7 @@ restore_vfp FUNCTION ; If r1 is 0, we assume that the OS is not using the Virtualization extensions, ; and that the warm boot code will set up CNTHCTL correctly. If r1 is non-zero ; then CNTHCTL is saved and restored - ; CNTP_CVAL will be preserved as it is in the always-on domain. + ; CNTP_CVAL will be preserved as it is in the always-on domain. save_generic_timer FUNCTION mrc p15,0,r2,c14,c2,1 ; read CNTP_CTL |