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authorEli Friedman <efriedma@quicinc.com>2019-05-14 21:44:54 +0000
committerEli Friedman <efriedma@quicinc.com>2019-05-14 21:44:54 +0000
commitc1985baed25b1a7dd45412cb6cc62c32ac5743d0 (patch)
treea636138d603fb2fef093dc98a5bd8e5846fe7d9c
parent8db7163070b885e918ab79314943bc3c1df12a7e (diff)
[OpenMP][AArch64] Fix compile with LLVM trunk.
The code is currently using the ambiguous instruction "sub sp, sp, w9, lsl #4". The ARM reference manual says this isn't valid, and it's not clear whether it's supposed to mean uxtw or uxtx. It doesn't matter which instruction we use here, since the high bits of the operand are zero anyway, so I arbitrarily choose uxtw, to preserve the register name. See https://reviews.llvm.org/D60840 for the LLVM patch. Differential Revision: https://reviews.llvm.org/D61770 git-svn-id: https://llvm.org/svn/llvm-project/openmp/trunk@360711 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--runtime/src/z_Linux_asm.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/runtime/src/z_Linux_asm.S b/runtime/src/z_Linux_asm.S
index 1197864..39bf427 100644
--- a/runtime/src/z_Linux_asm.S
+++ b/runtime/src/z_Linux_asm.S
@@ -1243,7 +1243,7 @@ __tid = 8
orr w9, wzr, #1
add w9, w9, w3, lsr #1
- sub sp, sp, w9, lsl #4
+ sub sp, sp, w9, uxtw #4
mov x11, sp
mov x8, x0