1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
define i64 @test1(i32 %xx, i32 %test) nounwind {
; CHECK-LABEL: test1:
; CHECK: # BB#0:
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: andb $7, %cl
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shll %cl, %eax
; CHECK-NEXT: shrl %edx
; CHECK-NEXT: xorb $31, %cl
; CHECK-NEXT: shrl %cl, %edx
; CHECK-NEXT: retl
%conv = zext i32 %xx to i64
%and = and i32 %test, 7
%sh_prom = zext i32 %and to i64
%shl = shl i64 %conv, %sh_prom
ret i64 %shl
}
define i64 @test2(i64 %xx, i32 %test) nounwind {
; CHECK-LABEL: test2:
; CHECK: # BB#0:
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: andb $7, %cl
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: shll %cl, %eax
; CHECK-NEXT: shldl %cl, %esi, %edx
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
%and = and i32 %test, 7
%sh_prom = zext i32 %and to i64
%shl = shl i64 %xx, %sh_prom
ret i64 %shl
}
define i64 @test3(i64 %xx, i32 %test) nounwind {
; CHECK-LABEL: test3:
; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: andb $7, %cl
; CHECK-NEXT: shrdl %cl, %edx, %eax
; CHECK-NEXT: shrl %cl, %edx
; CHECK-NEXT: retl
%and = and i32 %test, 7
%sh_prom = zext i32 %and to i64
%shr = lshr i64 %xx, %sh_prom
ret i64 %shr
}
define i64 @test4(i64 %xx, i32 %test) nounwind {
; CHECK-LABEL: test4:
; CHECK: # BB#0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: andb $7, %cl
; CHECK-NEXT: shrdl %cl, %edx, %eax
; CHECK-NEXT: sarl %cl, %edx
; CHECK-NEXT: retl
%and = and i32 %test, 7
%sh_prom = zext i32 %and to i64
%shr = ashr i64 %xx, %sh_prom
ret i64 %shr
}
; PR14668
define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) {
; CHECK-LABEL: test5:
; CHECK: # BB#0:
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 20
; CHECK-NEXT: .cfi_offset %esi, -20
; CHECK-NEXT: .cfi_offset %edi, -16
; CHECK-NEXT: .cfi_offset %ebx, -12
; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %ebx, %edi
; CHECK-NEXT: shll %cl, %edi
; CHECK-NEXT: shldl %cl, %ebx, %esi
; CHECK-NEXT: testb $32, %cl
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: je .LBB4_2
; CHECK-NEXT: # BB#1:
; CHECK-NEXT: movl %edi, %esi
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movl %edx, %ebx
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: shll %cl, %ebx
; CHECK-NEXT: shldl %cl, %edx, %ebp
; CHECK-NEXT: testb $32, %cl
; CHECK-NEXT: je .LBB4_4
; CHECK-NEXT: # BB#3:
; CHECK-NEXT: movl %ebx, %ebp
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: .LBB4_4:
; CHECK-NEXT: movl %ebp, 12(%eax)
; CHECK-NEXT: movl %ebx, 8(%eax)
; CHECK-NEXT: movl %esi, 4(%eax)
; CHECK-NEXT: movl %edi, (%eax)
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl $4
%shl = shl <2 x i64> %A, %B
ret <2 x i64> %shl
}
; PR16108
define i32 @test6() {
; CHECK-LABEL: test6:
; CHECK: # BB#0:
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: shldl $32, %eax, %ecx
; CHECK-NEXT: movb $32, %dl
; CHECK-NEXT: testb %dl, %dl
; CHECK-NEXT: jne .LBB5_2
; CHECK-NEXT: # BB#1:
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: sete %cl
; CHECK-NEXT: movzbl %cl, %ecx
; CHECK-NEXT: xorl $1, %eax
; CHECK-NEXT: orl %ecx, %eax
; CHECK-NEXT: je .LBB5_5
; CHECK-NEXT: # BB#3: # %if.then
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: jmp .LBB5_4
; CHECK-NEXT: .LBB5_5: # %if.end
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: .LBB5_4: # %if.then
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
%x = alloca i32, align 4
%t = alloca i64, align 8
store volatile i32 1, i32* %x, align 4
%load = load volatile i32, i32* %x, align 4
%shl = shl i32 %load, 8
%add = add i32 %shl, -224
%sh_prom = zext i32 %add to i64
%shl1 = shl i64 1, %sh_prom
%cmp = icmp ne i64 %shl1, 4294967296
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
ret i32 1
if.end: ; preds = %entry
ret i32 0
}
|
