1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
|
//===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file declares the targeting of the RegisterBankInfo class for AArch64.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#define GET_REGBANK_DECLARATIONS
#include "AArch64GenRegisterBank.inc"
namespace llvm {
class TargetRegisterInfo;
class AArch64GenRegisterBankInfo : public RegisterBankInfo {
protected:
enum PartialMappingIdx {
PMI_None = -1,
PMI_FPR16 = 1,
PMI_FPR32,
PMI_FPR64,
PMI_FPR128,
PMI_FPR256,
PMI_FPR512,
PMI_GPR32,
PMI_GPR64,
PMI_FirstGPR = PMI_GPR32,
PMI_LastGPR = PMI_GPR64,
PMI_FirstFPR = PMI_FPR16,
PMI_LastFPR = PMI_FPR512,
PMI_Min = PMI_FirstFPR,
};
static RegisterBankInfo::PartialMapping PartMappings[];
static RegisterBankInfo::ValueMapping ValMappings[];
static PartialMappingIdx BankIDToCopyMapIdx[];
enum ValueMappingIdx {
InvalidIdx = 0,
First3OpsIdx = 1,
Last3OpsIdx = 22,
DistanceBetweenRegBanks = 3,
FirstCrossRegCpyIdx = 25,
LastCrossRegCpyIdx = 39,
DistanceBetweenCrossRegCpy = 2,
FPExt16To32Idx = 41,
FPExt16To64Idx = 43,
FPExt32To64Idx = 45,
FPExt64To128Idx = 47,
};
static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
unsigned ValLength, const RegisterBank &RB);
static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
unsigned Size, unsigned Offset);
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
PartialMappingIdx LastAlias,
ArrayRef<PartialMappingIdx> Order);
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
/// Get the pointer to the ValueMapping representing the RegisterBank
/// at \p RBIdx with a size of \p Size.
///
/// The returned mapping works for instructions with the same kind of
/// operands for up to 3 operands.
///
/// \pre \p RBIdx != PartialMappingIdx::None
static const RegisterBankInfo::ValueMapping *
getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
/// Get the pointer to the ValueMapping of the operands of a copy
/// instruction from the \p SrcBankID register bank to the \p DstBankID
/// register bank with a size of \p Size.
static const RegisterBankInfo::ValueMapping *
getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
/// Get the instruction mapping for G_FPEXT.
///
/// \pre (DstSize, SrcSize) pair is one of the following:
/// (32, 16), (64, 16), (64, 32), (128, 64)
///
/// \return An InstructionMapping with statically allocated OperandsMapping.
static const RegisterBankInfo::ValueMapping *
getFPExtMapping(unsigned DstSize, unsigned SrcSize);
#define GET_TARGET_REGBANK_CLASS
#include "AArch64GenRegisterBank.inc"
};
/// This class provides the information for the target register banks.
class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
/// See RegisterBankInfo::applyMapping.
void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
/// Get an instruction mapping where all the operands map to
/// the same register bank and have similar size.
///
/// \pre MI.getNumOperands() <= 3
///
/// \return An InstructionMappings with a statically allocated
/// OperandsMapping.
const InstructionMapping &
getSameKindOfOperandsMapping(const MachineInstr &MI) const;
public:
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
unsigned Size) const override;
const RegisterBank &
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
InstructionMappings
getInstrAlternativeMappings(const MachineInstr &MI) const override;
const InstructionMapping &
getInstrMapping(const MachineInstr &MI) const override;
};
} // End llvm namespace.
#endif
|
