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authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2016-09-14 14:18:21 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2016-09-14 14:18:21 +0000
commit707666e59d26c30c077961eb36d52d87ff5bc47e (patch)
tree3b8e6499dbc0681e6d1e84e14474803da8e7e8d4 /test/Transforms/InstCombine/udiv-simplify.ll
parentf64fd3777c15b0145afeb57f62ca38bca97f4fed (diff)
[InstCombine] Merged two test files and regenerated checks using update_test_checks.py. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281478 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Transforms/InstCombine/udiv-simplify.ll')
-rw-r--r--test/Transforms/InstCombine/udiv-simplify.ll49
1 files changed, 49 insertions, 0 deletions
diff --git a/test/Transforms/InstCombine/udiv-simplify.ll b/test/Transforms/InstCombine/udiv-simplify.ll
new file mode 100644
index 00000000000..296821f704c
--- /dev/null
+++ b/test/Transforms/InstCombine/udiv-simplify.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i64 @test1(i32 %x) nounwind {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: ret i64 0
+;
+ %y = lshr i32 %x, 1
+ %r = udiv i32 %y, -1
+ %z = sext i32 %r to i64
+ ret i64 %z
+}
+define i64 @test2(i32 %x) nounwind {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: ret i64 0
+;
+ %y = lshr i32 %x, 31
+ %r = udiv i32 %y, 3
+ %z = sext i32 %r to i64
+ ret i64 %z
+}
+
+; The udiv instructions shouldn't be optimized away, and the
+; sext instructions should be optimized to zext.
+
+define i64 @test1_PR2274(i32 %x, i32 %g) nounwind {
+; CHECK-LABEL: @test1_PR2274(
+; CHECK-NEXT: [[Y:%.*]] = lshr i32 %x, 30
+; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], %g
+; CHECK-NEXT: [[Z1:%.*]] = zext i32 [[R]] to i64
+; CHECK-NEXT: ret i64 [[Z1]]
+;
+ %y = lshr i32 %x, 30
+ %r = udiv i32 %y, %g
+ %z = sext i32 %r to i64
+ ret i64 %z
+}
+define i64 @test2_PR2274(i32 %x, i32 %v) nounwind {
+; CHECK-LABEL: @test2_PR2274(
+; CHECK-NEXT: [[Y:%.*]] = lshr i32 %x, 31
+; CHECK-NEXT: [[R:%.*]] = udiv i32 [[Y]], %v
+; CHECK-NEXT: [[Z1:%.*]] = zext i32 [[R]] to i64
+; CHECK-NEXT: ret i64 [[Z1]]
+;
+ %y = lshr i32 %x, 31
+ %r = udiv i32 %y, %v
+ %z = sext i32 %r to i64
+ ret i64 %z
+}