Canonicalize a large number of mir tests using update_mir_test_checks

This converts a large and somewhat arbitrary set of tests to use
update_mir_test_checks. I ran the script on all of the tests I expect
to need to modify for an upcoming mir syntax change and kept the ones
that obviously didn't change the tests in ways that might make it
harder to understand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316137 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 403 insertions, 650 deletions

diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
index 6c8bc7123a1..8f1d4d1d546 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 --- |
   define void @test_icmp_eq_s32() { ret void }
@@ -53,11 +54,9 @@
 ...
 ---
 name:            test_icmp_eq_s32
-# CHECK-LABEL: name: test_icmp_eq_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -67,33 +66,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_eq_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(eq),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_icmp_ne_s32
-# CHECK-LABEL: name: test_icmp_ne_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -103,33 +96,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_ne_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(ne),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_icmp_ugt_s32
-# CHECK-LABEL: name: test_icmp_ugt_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -139,33 +126,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_ugt_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(ugt),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_icmp_uge_s32
-# CHECK-LABEL: name: test_icmp_uge_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -175,33 +156,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_uge_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 2, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(uge),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 2, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_icmp_ult_s32
-# CHECK-LABEL: name: test_icmp_ult_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -211,33 +186,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_ult_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 3, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(ult),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 3, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_icmp_ule_s32
-# CHECK-LABEL: name: test_icmp_ule_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -247,33 +216,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_ule_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(ule),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_icmp_sgt_s32
-# CHECK-LABEL: name: test_icmp_sgt_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -283,33 +246,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_sgt_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(sgt),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_icmp_sge_s32
-# CHECK-LABEL: name: test_icmp_sge_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -319,33 +276,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_sge_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(sge),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_icmp_slt_s32
-# CHECK-LABEL: name: test_icmp_slt_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -355,33 +306,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_slt_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(slt),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_icmp_sle_s32
-# CHECK-LABEL: name: test_icmp_sle_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
@@ -391,33 +336,27 @@ body:             |
   bb.0:
     liveins: %r0, %r1
 
+    ; CHECK-LABEL: name: test_icmp_sle_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %r0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %r1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, _, implicit-def %cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %r0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
-
     %1(s32) = COPY %r1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
-
     %2(s1) = G_ICMP intpred(sle),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: CMPrr [[VREGX]], [[VREGY]], 14, _, implicit-def %cpsr
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_true_s32
-# CHECK-LABEL: name: test_fcmp_true_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -427,28 +366,23 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_true_s32
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 1, 14, _, _
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
-
     %2(s1) = G_FCMP floatpred(true),  %0(s32), %1
-    ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_false_s32
-# CHECK-LABEL: name: test_fcmp_false_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -458,28 +392,23 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_false_s32
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
     %1(s32) = COPY %s1
-
     %2(s1) = G_FCMP floatpred(false),  %0(s32), %1
-    ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_oeq_s32
-# CHECK-LABEL: name: test_fcmp_oeq_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -489,34 +418,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_oeq_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(oeq),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ogt_s32
-# CHECK-LABEL: name: test_fcmp_ogt_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -526,34 +449,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_ogt_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(ogt),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_oge_s32
-# CHECK-LABEL: name: test_fcmp_oge_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -563,34 +480,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_oge_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(oge),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_olt_s32
-# CHECK-LABEL: name: test_fcmp_olt_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -600,34 +511,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_olt_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 4, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(olt),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ole_s32
-# CHECK-LABEL: name: test_fcmp_ole_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -637,34 +542,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_ole_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(ole),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ord_s32
-# CHECK-LABEL: name: test_fcmp_ord_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -674,34 +573,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_ord_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 7, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(ord),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ugt_s32
-# CHECK-LABEL: name: test_fcmp_ugt_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -711,34 +604,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_ugt_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(ugt),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_uge_s32
-# CHECK-LABEL: name: test_fcmp_uge_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -748,34 +635,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_uge_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 5, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(uge),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ult_s32
-# CHECK-LABEL: name: test_fcmp_ult_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -785,34 +666,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_ult_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(ult),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ule_s32
-# CHECK-LABEL: name: test_fcmp_ule_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -822,34 +697,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_ule_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(ule),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_une_s32
-# CHECK-LABEL: name: test_fcmp_une_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -859,34 +728,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_une_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(une),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_uno_s32
-# CHECK-LABEL: name: test_fcmp_uno_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -896,34 +759,28 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_uno_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 6, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(uno),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_one_s32
-# CHECK-LABEL: name: test_fcmp_one_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -933,37 +790,31 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_one_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 4, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(one),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ueq_s32
-# CHECK-LABEL: name: test_fcmp_ueq_s32
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -973,37 +824,31 @@ body:             |
   bb.0:
     liveins: %s0, %s1
 
+    ; CHECK-LABEL: name: test_fcmp_ueq_s32
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %s0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 6, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s32) = COPY %s0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %s0
-
     %1(s32) = COPY %s1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %s1
-
     %2(s1) = G_FCMP floatpred(ueq),  %0(s32), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
-    ; CHECK-NEXT: VCMPS [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_true_s64
-# CHECK-LABEL: name: test_fcmp_true_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1013,28 +858,23 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_true_s64
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 1, 14, _, _
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
-
     %2(s1) = G_FCMP floatpred(true),  %0(s64), %1
-    ; CHECK: [[RES:%[0-9]+]] = MOVi 1, 14, _, _
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_false_s64
-# CHECK-LABEL: name: test_fcmp_false_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1044,28 +884,23 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_false_s64
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
     %1(s64) = COPY %d1
-
     %2(s1) = G_FCMP floatpred(false),  %0(s64), %1
-    ; CHECK: [[RES:%[0-9]+]] = MOVi 0, 14, _, _
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_oeq_s64
-# CHECK-LABEL: name: test_fcmp_oeq_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1075,34 +910,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_oeq_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(oeq),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ogt_s64
-# CHECK-LABEL: name: test_fcmp_ogt_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1112,34 +941,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_ogt_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(ogt),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_oge_s64
-# CHECK-LABEL: name: test_fcmp_oge_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1149,34 +972,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_oge_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 10, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(oge),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 10, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_olt_s64
-# CHECK-LABEL: name: test_fcmp_olt_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1186,34 +1003,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_olt_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 4, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(olt),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 4, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ole_s64
-# CHECK-LABEL: name: test_fcmp_ole_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1223,34 +1034,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_ole_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 9, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(ole),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 9, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ord_s64
-# CHECK-LABEL: name: test_fcmp_ord_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1260,34 +1065,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_ord_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 7, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(ord),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 7, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ugt_s64
-# CHECK-LABEL: name: test_fcmp_ugt_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1297,34 +1096,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_ugt_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 8, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(ugt),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 8, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_uge_s64
-# CHECK-LABEL: name: test_fcmp_uge_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1334,34 +1127,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_uge_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 5, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(uge),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 5, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ult_s64
-# CHECK-LABEL: name: test_fcmp_ult_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1371,34 +1158,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_ult_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 11, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(ult),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 11, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ule_s64
-# CHECK-LABEL: name: test_fcmp_ule_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1408,34 +1189,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_ule_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 13, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(ule),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 13, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_une_s64
-# CHECK-LABEL: name: test_fcmp_une_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1445,34 +1220,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_une_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 1, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(une),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 1, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_uno_s64
-# CHECK-LABEL: name: test_fcmp_uno_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1482,34 +1251,28 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_uno_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 6, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(uno),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[ZERO]], 1, 6, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_one_s64
-# CHECK-LABEL: name: test_fcmp_one_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1519,37 +1282,31 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_one_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 12, %cpsr
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 4, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(one),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 12, %cpsr
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 4, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...
 ---
 name:            test_fcmp_ueq_s64
-# CHECK-LABEL: name: test_fcmp_ueq_s64
 legalized:       true
 regBankSelected: true
 selected:        false
-# CHECK: selected: true
 registers:
   - { id: 0, class: fprb }
   - { id: 1, class: fprb }
@@ -1559,27 +1316,23 @@ body:             |
   bb.0:
     liveins: %d0, %d1
 
+    ; CHECK-LABEL: name: test_fcmp_ueq_s64
+    ; CHECK: [[COPY:%[0-9]+]] = COPY %d0
+    ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1
+    ; CHECK: [[MOVi:%[0-9]+]] = MOVi 0, 14, _, _
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi:%[0-9]+]] = MOVCCi [[MOVi]], 1, 0, %cpsr
+    ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, _, implicit-def %fpscr_nzcv
+    ; CHECK: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
+    ; CHECK: [[MOVCCi1:%[0-9]+]] = MOVCCi [[MOVCCi]], 1, 6, %cpsr
+    ; CHECK: [[ANDri:%[0-9]+]] = ANDri [[MOVCCi1]], 1, 14, _, _
+    ; CHECK: %r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, _, implicit %r0
     %0(s64) = COPY %d0
-    ; CHECK: [[VREGX:%[0-9]+]] = COPY %d0
-
     %1(s64) = COPY %d1
-    ; CHECK: [[VREGY:%[0-9]+]] = COPY %d1
-
     %2(s1) = G_FCMP floatpred(ueq),  %0(s64), %1
-    ; CHECK: [[ZERO:%[0-9]+]] = MOVi 0, 14, _, _
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES1:%[0-9]+]] = MOVCCi [[ZERO]], 1, 0, %cpsr
-    ; CHECK-NEXT: VCMPD [[VREGX]], [[VREGY]], 14, _, implicit-def %fpscr_nzcv
-    ; CHECK-NEXT: FMSTAT 14, _, implicit-def %cpsr, implicit %fpscr_nzcv
-    ; CHECK-NEXT: [[RES:%[0-9]+]] = MOVCCi [[RES1]], 1, 6, %cpsr
-
     %3(s32) = G_ZEXT %2(s1)
-    ; CHECK: [[RET:%[0-9]+]] = ANDri [[RES]], 1, 14, _, _
-
     %r0 = COPY %3(s32)
-    ; CHECK: %r0 = COPY [[RET]]
-
     BX_RET 14, _, implicit %r0
-    ; CHECK: BX_RET 14, _, implicit %r0
 ...