diff options
| author | H.J. Lu <hjl.tools@gmail.com> | 2022-01-14 14:48:01 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2022-02-01 07:28:00 -0800 |
| commit | 76e30dd44ef7aab743a538dcd4a81761a1f612d9 (patch) | |
| tree | b54d7451e3a2e29d30b36dad23b19be69fc620a5 | |
| parent | 071e2bdd850de9387b22b387f5f42e5c7d6668de (diff) | |
x86: Black list more Intel CPUs for TSX [BZ #27398]
Disable TSX and enable RTM_ALWAYS_ABORT for Intel CPUs listed in:
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
This fixes BZ #27398.
Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
(cherry picked from commit 1e000d3d33211d5a954300e2a69b90f93f18a1a1)
| -rw-r--r-- | sysdeps/x86/cpu-features.c | 37 |
1 files changed, 34 insertions, 3 deletions
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 00ca2fe82d..91215f8e23 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -397,11 +397,42 @@ init_cpu_features (struct cpu_features *cpu_features) break; } - /* Disable TSX on some Haswell processors to avoid TSX on kernels that - weren't updated with the latest microcode package (which disables - broken feature by default). */ + /* Disable TSX on some processors to avoid TSX on kernels that + weren't updated with the latest microcode package (which + disables broken feature by default). */ switch (model) { + case 0x55: + if (stepping <= 5) + goto disable_tsx; + break; + case 0x8e: + /* NB: Although the errata documents that for model == 0x8e, + only 0xb stepping or lower are impacted, the intention of + the errata was to disable TSX on all client processors on + all steppings. Include 0xc stepping which is an Intel + Core i7-8665U, a client mobile processor. */ + case 0x9e: + if (stepping > 0xc) + break; + /* Fall through. */ + case 0x4e: + case 0x5e: + { + /* Disable Intel TSX and enable RTM_ALWAYS_ABORT for + processors listed in: + +https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html + */ +disable_tsx: + cpu_features->cpuid[index_cpu_HLE].reg_HLE + &= ~bit_cpu_HLE; + cpu_features->cpuid[index_cpu_RTM].reg_RTM + &= ~bit_cpu_RTM; + cpu_features->cpuid[index_cpu_RTM_ALWAYS_ABORT].reg_RTM_ALWAYS_ABORT + |= bit_cpu_RTM_ALWAYS_ABORT; + } + break; case 0x3f: /* Xeon E7 v3 with stepping >= 4 has working TSX. */ if (stepping >= 4) |