| Age | Commit message (Expand) | Author |
|---|
| 2018-01-16 | Update translations for various binutils components. | Nick Clifton |
| 2018-01-15 | RISC-V: Add support for addi that compresses to c.nop. | Jim Wilson |
| 2018-01-15 | [ARM] Add new macro for Thumb-only opcodes | Thomas Preud'homme |
| 2018-01-15 | [ARM] Enable conditional Armv8-M instructions | Thomas Preud'homme |
| 2018-01-15 | [ARM] No IT usage deprecation for ARMv8-M | Thomas Preud'homme |
| 2018-01-15 | Update Ukranian translations for bfd, binutils, gas, gold, ld and opcodes | Nick Clifton |
| 2018-01-13 | Update pot files | Nick Clifton |
| 2018-01-13 | Bump version number to 2.30.51 | Nick Clifton |
| 2018-01-13 | Add note about 2.30 branch creation to changelogs | Nick Clifton |
| 2018-01-13 | Add 2.30 markers to NEWS files. | Nick Clifton |
| 2018-01-12 | Fix compile time warning building aout targeted architectures. | Gunther Nikl |
| 2018-01-11 | Remove VL variants for 4FMAPS and 4VNNIW insns. | Igor Tsimbalist |
| 2018-01-11 | gas tc-arm.c warning fix | Alan Modra |
| 2018-01-10 | x86: fix Disp8 handling for scalar AVX512_4FMAPS insns | Jan Beulich |
| 2018-01-10 | x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants | Jan Beulich |
| 2018-01-09 | RISC-V: Disassemble x0 based addresses as 0. | Jim Wilson |
| 2018-01-09 | [Arm] Add CSDB instruction | James Greenhalgh |
| 2018-01-09 | Add support for the AArch64's CSDB instruction. | James Greenhalgh |
| 2018-01-08 | x86: Properly encode vmovd with 64-bit memeory | H.J. Lu |
| 2018-01-08 | Add a description of the X86_64 assembler's .largcomm pseudo-op. | Nick Clifton |
| 2018-01-04 | RISC-V: Add 2 missing privileged registers. | Jim Wilson |
| 2018-01-03 | Update year range in copyright notice of binutils files | Alan Modra |
| 2018-01-03 | ChangeLog rotation | Alan Modra |
| 2018-01-02 | Fix typo in do_mrs function in ARM assembler. | Nick Clifton |
| 2017-12-28 | RISC-V: Add missing privileged spec registers. | Jim Wilson |
| 2017-12-20 | RISC-V: Add compressed instruction hints, and a few misc cleanups. | Jim Wilson |
| 2017-12-19 | Correct disassembly of dot product instructions. | Tamar Christina |
| 2017-12-19 | Add support for V_4B so we can properly reject it. | Tamar Christina |
| 2017-12-18 | Resolve PR 22493 - the encoding to be used when pushing the stack pointer ont... | Nick Clifton |
| 2017-12-18 | x86: fold certain AVX and AVX2 templates | Jan Beulich |
| 2017-12-18 | x86: fold RegXMM/RegYMM/RegZMM into RegSIMD | Jan Beulich |
| 2017-12-18 | x86: drop FloatReg and FloatAcc | Jan Beulich |
| 2017-12-18 | x86: replace Reg8, Reg16, Reg32, and Reg64 | Jan Beulich |
| 2017-12-17 | x86: Check pseudo prefix without instruction | H.J. Lu |
| 2017-12-15 | x86: correct operand type checks | Jan Beulich |
| 2017-12-15 | x86: correct abort check | Jan Beulich |
| 2017-12-14 | Update the address of the FSF in the copyright notice of files which were usi... | Nick Clifton |
| 2017-12-13 | Add missing RISC-V fsrmi and fsflagsi instructions. | Jim Wilson |
| 2017-12-13 | This patch enables disassembler_needs_relocs for PRU. It is needed to print c... | Dimitar Dimitrov |
| 2017-12-12 | Don't mask X_add_number containing a register number | Alan Modra |
| 2017-12-08 | gas: xtensa: fix comparison of trampoline chain symbols | Max Filippov |
| 2017-12-04 | Documentation fix | Alan Modra |
| 2017-12-04 | Run powerpc vle gas tests for all powerpc ELF targets | Alan Modra |
| 2017-12-03 | Fix for texinfo 4.8. | Jim Wilson |
| 2017-12-01 | Update and clean up RISC-V gas documentation. | Jim Wilson |
| 2017-12-01 | Use consistent types for holding instructions, instruction masks, etc. | Peter Bergner |
| 2017-11-30 | x86: drop Vec_Disp8 | Jan Beulich |
| 2017-11-30 | x86/Intel: issue diagnostics for redundant segment override prefixes | Jan Beulich |
| 2017-11-30 | Revert "x86: Update segment register check in Intel syntax" | Jan Beulich |
| 2017-11-29 | Give Palmer co-credit for last patch. | Jim Wilson |
