diff options
| author | Francesco Lavra <francescolavra.fl@gmail.com> | 2013-06-24 20:21:52 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-16 17:51:45 +0000 |
| commit | b8813fe7aef3a8042e8cf13e4e9401c6caf591a9 (patch) | |
| tree | 9c10499b763eac63d863b87623d8e843f77261a5 | |
| parent | 3a91144ad85467fa56ff86c5c9dc2787a711f109 (diff) | |
omap_i2c: don't end I2C transfer immediately when STP bit is set2014.01.rebasing
When the OMAP I2C controller is operated in master mode, setting the
STP bit in the CON register instructs the controller to generate an I2C
stop condition only after the programmed number of bytes has been sent
on the I2C bus. The current code in QEMU ends the I2C transfer without
first sending the pending data instead.
Fix the above issue, and let the I2C transfer be ended in
omap_i2c_fifo_run(), after the count of bytes to send has reached zero.
Signed-off-by: Francesco Lavra <francescolavra.fl@gmail.com>
| -rw-r--r-- | hw/i2c/omap_i2c.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c index 353ca46f9..9de2510a0 100644 --- a/hw/i2c/omap_i2c.c +++ b/hw/i2c/omap_i2c.c @@ -527,10 +527,6 @@ static void omap_i2c_write(void *opaque, hwaddr addr, omap_i2c_fifo_run(s); } omap_i2c_interrupts_update(s); - } else if (value & 2) { /* STP, but not STT */ - i2c_end_transfer(s->bus); - s->control &= ~0x0602; /* MST | TRX | STP */ - s->count_cur = s->count; } } break; |