diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2011-08-12 11:45:26 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2011-08-12 11:50:06 +0000 |
| commit | 102665fd1a1df0c0366ba54a0b540a45eb4ea455 (patch) | |
| tree | bf12657aaa406405d62652bf4d83ab041be25459 | |
| parent | dab4da8a574e7b78479f6a58c37fa900f44e8e98 (diff) | |
hw/omap_i2c: Treat 32 bit accesses like 16 bit accesses2011.08.rebasing
Treat 32 bit OMAP i2c register accesses like 16 bit accesses, working
around the kernel bug LP:727781 where it makes 32 bit accesses in violation
of the TRM. (Hardware behaviour is apparently that OMAP2 will abort on
these 32 bit accesses, but OMAP3 and 4 will allow them.)
We might need to revert or rethink this patch as part of handling silencing
of bad-kernel-behaviour warnings more consistently so that they can be
upstreamed.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/omap_i2c.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c index d280a0f3c..98f9ea5a5 100644 --- a/hw/omap_i2c.c +++ b/hw/omap_i2c.c @@ -669,13 +669,13 @@ static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr, static CPUReadMemoryFunc * const omap_i2c_readfn[] = { omap_i2c_readb, omap_i2c_read, - omap_badwidth_read16, + omap_i2c_read, }; static CPUWriteMemoryFunc * const omap_i2c_writefn[] = { omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */ omap_i2c_write, - omap_badwidth_write16, + omap_i2c_write, }; static int omap_i2c_bus_post_load(void *opaque, int version_id) |