diff options
| author | Sekhar Nori <nsekhar@ti.com> | 2012-06-20 23:10:13 +0530 |
|---|---|---|
| committer | Sekhar Nori <nsekhar@ti.com> | 2012-07-09 16:01:11 +0530 |
| commit | bbb33445b9cdd5ac7609723fcfc28dfa77a11039 (patch) | |
| tree | 0e5a43af51fafdc94482fd502f9107357064c73e | |
| parent | 485802a6c524e62b5924849dd727ddbb1497cc71 (diff) | |
ARM: davinci: da8xx: fix interrupt handlingdavinci-v3.6-fixes
CP_INTC code in entry-macro.S code reads SECR1n register to see if
an interrupt was indeed pending. This register is actually marked as
write-only in the OMAP-L138 TRM. Moreover, the code just checks to see
the entire register is non-zero and does not check a specific interrupt
number.
Fix this to use interrupt pending bit in GIPR register for this purpose.
GIPR register is already being read to know the highest priority interrupt
pending.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| -rw-r--r-- | arch/arm/mach-davinci/include/mach/entry-macro.S | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S index 768b3c060214..cf5f573eb5fd 100644 --- a/arch/arm/mach-davinci/include/mach/entry-macro.S +++ b/arch/arm/mach-davinci/include/mach/entry-macro.S @@ -30,12 +30,10 @@ #endif #if defined(CONFIG_CP_INTC) 1001: ldr \irqnr, [\base, #0x80] /* get irq number */ + mov \tmp, \irqnr, lsr #31 and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */ - mov \tmp, \irqnr, lsr #3 - and \tmp, \tmp, #0xfc - add \tmp, \tmp, #0x280 /* get the register offset */ - ldr \irqstat, [\base, \tmp] /* get the intc status */ - cmp \irqstat, #0x0 + and \tmp, \tmp, #0x1 + cmp \tmp, #0x1 #endif 1002: .endm |