diff options
author | Alex Bennée <alex.bennee@linaro.org> | 2018-06-22 15:11:59 +0100 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2018-07-02 13:08:21 +0100 |
commit | 44c6937c23ef60dd70b799024da41f2694ff715e (patch) | |
tree | aab3dc4253735fad89dcd5c89223c5146642f793 | |
parent | 774d0fe84d75e252fd0595ca7924838d5b0fbd71 (diff) |
risu_reginfo_aarch64: unionify VFP regs
This is preparation for the SVE work as we won't want to be carrying
around both VFP and SVE registers at the same time as they overlap.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180622141205.16306-17-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | risu_reginfo_aarch64.c | 16 | ||||
-rw-r--r-- | risu_reginfo_aarch64.h | 9 |
2 files changed, 16 insertions, 9 deletions
diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 34dd9af..62a5599 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -64,7 +64,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) ri->fpcr = fp->fpcr; for (i = 0; i < 32; i++) { - ri->vregs[i] = fp->vregs[i]; + ri->simd.vregs[i] = fp->vregs[i]; } } @@ -92,8 +92,8 @@ int reginfo_dump(struct reginfo *ri, FILE * f) for (i = 0; i < 32; i++) { fprintf(f, " V%2d : %016" PRIx64 "%016" PRIx64 "\n", i, - (uint64_t) (ri->vregs[i] >> 64), - (uint64_t) (ri->vregs[i] & 0xffffffffffffffff)); + (uint64_t) (ri->simd.vregs[i] >> 64), + (uint64_t) (ri->simd.vregs[i] & 0xffffffffffffffff)); } return !ferror(f); @@ -138,14 +138,14 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) } for (i = 0; i < 32; i++) { - if (m->vregs[i] != a->vregs[i]) { + if (m->simd.vregs[i] != a->simd.vregs[i]) { fprintf(f, " V%2d : " "%016" PRIx64 "%016" PRIx64 " vs " "%016" PRIx64 "%016" PRIx64 "\n", i, - (uint64_t) (m->vregs[i] >> 64), - (uint64_t) (m->vregs[i] & 0xffffffffffffffff), - (uint64_t) (a->vregs[i] >> 64), - (uint64_t) (a->vregs[i] & 0xffffffffffffffff)); + (uint64_t) (m->simd.vregs[i] >> 64), + (uint64_t) (m->simd.vregs[i] & 0xffffffffffffffff), + (uint64_t) (a->simd.vregs[i] >> 64), + (uint64_t) (a->simd.vregs[i] & 0xffffffffffffffff)); } } diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index a05fb4e..a1c708b 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -13,6 +13,10 @@ #ifndef RISU_REGINFO_AARCH64_H #define RISU_REGINFO_AARCH64_H +struct simd_reginfo { + __uint128_t vregs[32]; +}; + struct reginfo { uint64_t fault_address; uint64_t regs[31]; @@ -24,7 +28,10 @@ struct reginfo { /* FP/SIMD */ uint32_t fpsr; uint32_t fpcr; - __uint128_t vregs[32]; + + union { + struct simd_reginfo simd; + }; }; #endif /* RISU_REGINFO_AARCH64_H */ |