diff options
Diffstat (limited to 'arch')
30 files changed, 124 insertions, 586 deletions
diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAA b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAA index 706c756fc..b63ab6848 100644 --- a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAA +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAA @@ -12,12 +12,6 @@ config SOC string default nRF51822_QFAA -config SRAM_SIZE - default 16 - -config FLASH_SIZE - default 256 - config ISR_STACK_SIZE default 640 diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAB b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAB index e3476627a..c282c97da 100644 --- a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAB +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAB @@ -12,12 +12,6 @@ config SOC string default nRF51822_QFAB -config SRAM_SIZE - default 16 - -config FLASH_SIZE - default 128 - config ISR_STACK_SIZE default 640 diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAC b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAC index 5e6694457..e373d54dc 100644 --- a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAC +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.nrf51822_QFAC @@ -12,10 +12,4 @@ config SOC string default nRF51822_QFAC -config SRAM_SIZE - default 32 - -config FLASH_SIZE - default 256 - endif # SOC_NRF51822_QFAC diff --git a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.series b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.series index bf697eb5d..632bc9d7f 100644 --- a/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.series +++ b/arch/arm/soc/nordic_nrf5/nrf51/Kconfig.defconfig.series @@ -19,20 +19,10 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_POWER_MANAGEMENT default y -config SRAM_BASE_ADDRESS - default 0x20000000 - -config FLASH_BASE_ADDRESS - default 0x00000000 - config NUM_IRQS int default 26 -config NUM_IRQ_PRIO_BITS - int - default 2 - if SENSOR config TEMP_NRF5 diff --git a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832_QFAA b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832_QFAA index 73a2b69d3..ec4703b2a 100644 --- a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832_QFAA +++ b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832_QFAA @@ -12,14 +12,6 @@ config SOC string default nRF52832_QFAA -if !HAS_DTS -config SRAM_SIZE - default 64 - -config FLASH_SIZE - default 512 -endif - config NUM_IRQS int default 39 diff --git a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52840_QIAA b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52840_QIAA index 63435486a..abedef9df 100644 --- a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52840_QIAA +++ b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52840_QIAA @@ -12,12 +12,6 @@ config SOC string default nRF52840_QIAA -config SRAM_SIZE - default 256 - -config FLASH_SIZE - default 1024 - config NUM_IRQS int default 46 diff --git a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series index acbcf7c60..e46e932a9 100644 --- a/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series +++ b/arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series @@ -19,16 +19,4 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config SYS_POWER_MANAGEMENT default y -if !HAS_DTS -config SRAM_BASE_ADDRESS - default 0x20000000 - -config FLASH_BASE_ADDRESS - default 0x00000000 - -config NUM_IRQ_PRIO_BITS - int - default 3 -endif - endif # SOC_SERIES_NRF52X diff --git a/arch/arm/soc/nxp_kinetis/Kconfig b/arch/arm/soc/nxp_kinetis/Kconfig index 4bb558eb9..ceb58e7d9 100644 --- a/arch/arm/soc/nxp_kinetis/Kconfig +++ b/arch/arm/soc/nxp_kinetis/Kconfig @@ -58,6 +58,12 @@ config HAS_LPUART help Set if the low power uart (LPUART) module is present in the SoC. +config HAS_LPSCI + bool + default n + help + Set if the low power uart (LPSCI) module is present in the SoC. + if HAS_OSC choice diff --git a/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 b/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 index 22b9a69e2..c74f64ff9 100644 --- a/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 +++ b/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 @@ -31,7 +31,7 @@ endif # GPIO if SERIAL -config UART_MCUX +config UART_MCUX_LPSCI def_bool y endif # SERIAL diff --git a/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.soc b/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.soc index cedbb27f6..8081d9719 100644 --- a/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.soc +++ b/arch/arm/soc/nxp_kinetis/kl2x/Kconfig.soc @@ -15,6 +15,7 @@ config SOC_MKL25Z4 select HAS_MCUX select HAS_OSC select HAS_MCG + select HAS_LPSCI endchoice diff --git a/arch/arm/soc/nxp_kinetis/kl2x/soc.c b/arch/arm/soc/nxp_kinetis/kl2x/soc.c index d37778501..11a15c788 100644 --- a/arch/arm/soc/nxp_kinetis/kl2x/soc.c +++ b/arch/arm/soc/nxp_kinetis/kl2x/soc.c @@ -13,6 +13,8 @@ #include <fsl_clock.h> #include <arch/cpu.h> +#define LPSCI0SRC_MCGFLLCLK (1) + /******************************************************************************* * Variables ******************************************************************************/ @@ -93,8 +95,8 @@ static ALWAYS_INLINE void clkInit(void) CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow, 0); CLOCK_SetSimConfig(&simConfig); -#ifdef CONFIG_UART_MCUX_0 - CLOCK_SetLpsci0Clock(1); +#ifdef CONFIG_UART_MCUX_LPSCI_0 + CLOCK_SetLpsci0Clock(LPSCI0SRC_MCGFLLCLK); #endif } diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series index f25719859..cc581d520 100644 --- a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series +++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series @@ -42,7 +42,7 @@ endif #SERIAL if CLOCK_CONTROL -config CLOCK_CONTROL_STM32F4X +config CLOCK_CONTROL_STM32_CUBE def_bool y endif #CLOCK_CONTROL diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc b/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc index 7cc99c4d3..01e9d6d9c 100644 --- a/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc +++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc @@ -12,12 +12,12 @@ depends on SOC_SERIES_STM32F4X config SOC_STM32F401XE bool "STM32F401XE" -config SOC_STM32F411XE - bool "STM32F411XE" - config SOC_STM32F407XX bool "STM32F407XX" +config SOC_STM32F411XE + bool "STM32F411XE" + config SOC_STM32F429XX bool "STM32F429XX" diff --git a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h index 8b9ae4e7b..67c887348 100644 --- a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h +++ b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h @@ -15,15 +15,6 @@ * Chapter 3.4: Embedded Flash Memory */ -enum { - STM32F4X_FLASH_LATENCY_0 = 0x0, - STM32F4X_FLASH_LATENCY_1 = 0x1, - STM32F4X_FLASH_LATENCY_2 = 0x2, - STM32F4X_FLASH_LATENCY_3 = 0x3, - STM32F4X_FLASH_LATENCY_4 = 0x4, - STM32F4X_FLASH_LATENCY_5 = 0x5, -}; - union __flash_acr { u32_t val; struct { @@ -48,102 +39,4 @@ struct stm32f4x_flash { volatile u32_t optctrl; }; -/** - * @brief setup embedded flash controller - * - * Configure flash access time latency (wait states) depending on - * SYSCLK. This code assumes that we're using a supply voltage of - * 2.7V or higher, for lower voltages this code must be changed. - * - * The following tables show the required latency value required for a - * certain CPU frequency (HCLK) and supply voltage. See the section - * "Relation between CPU clock frequency and Flash memory read time" - * in the reference manual for more information. - * - * Note that the highest frequency might be limited for other reaasons - * than wait states, for example the STM32F405xx is limited to 168MHz - * even with 5 wait states and the highest supply voltage. - * - * STM32F401xx: - * - * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V - * ------- | ----------- | ----------- | ----------- | ----------- - * 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz - * 1 | 60 MHz | 48 MHz | 36 MHz | 32 MHz - * 2 | 84 MHz | 72 MHz | 54 MHz | 48 MHz - * 3 | | 84 MHz | 72 MHz | 64 MHz - * 4 | | | 84 MHz | 80 MHz - * 5 | | | | 84 MHz - * - * STM32F405xx/407xx/415xx/417xx/42xxx/43xxx: - * - * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V - * ------- | ----------- | ----------- | ----------- | ----------- - * 0 | 30 MHz | 24 MHz | 22 MHz | 20 MHz - * 1 | 60 MHz | 48 MHz | 44 MHz | 40 MHz - * 2 | 90 MHz | 72 MHz | 66 MHz | 60 MHz - * 3 | 120 MHz | 96 MHz | 88 MHz | 80 MHz - * 4 | 150 MHz | 120 MHz | 110 MHz | 100 MHz - * 5 | 180 MHz | 144 MHz | 132 MHz | 120 MHz - * 6 | | 168 MHz | 154 MHz | 140 MHz - * 7 | | 180 MHz | 176 MHz | 160 MHz - * 8 | | | 180 MHz | 168 MHz - * - * STM32F411x: - * - * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.7V - 2.1V - * ------- | ----------- | ----------- | ----------- | ----------- - * 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz - * 1 | 64 MHz | 48 MHz | 36 MHz | 32 MHz - * 2 | 90 MHz | 72 MHz | 54 MHz | 48 MHz - * 3 | 100 MHz | 96 MHz | 72 MHz | 64 MHz - * 4 | | 100 MHz | 90 MHz | 80 MHz - * 5 | | | 100 MHz | 96 MHz - * 6 | | | | 100 MHz - */ -static inline void __setup_flash(void) -{ - volatile struct stm32f4x_flash *regs; - u32_t tmpreg = 0; - - regs = (struct stm32f4x_flash *) FLASH_R_BASE; - - if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 30000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_0; - } -#ifdef CONFIG_SOC_STM32F401XE - else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 84000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2; - } -#elif CONFIG_SOC_STM32F411XE - else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 64000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 100000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3; - } -#elif defined(CONFIG_SOC_STM32F407XX) || defined(CONFIG_SOC_STM32F429XX) - else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 120000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 150000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_4; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 180000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_5; - } -#else -#error Flash latency configuration for MCU model is missing -#endif - - /* Make sure latency was set */ - tmpreg = regs->acr.bit.latency; - -} - #endif /* _STM32F4X_FLASHREGISTERS_H_ */ diff --git a/arch/arm/soc/st_stm32/stm32f4/rcc_registers.h b/arch/arm/soc/st_stm32/stm32f4/rcc_registers.h deleted file mode 100644 index 6cd0a97bf..000000000 --- a/arch/arm/soc/st_stm32/stm32f4/rcc_registers.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2016 Linaro Limited. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _STM32F4X_CLOCK_H_ -#define _STM32F4X_CLOCK_H_ - -/** - * @brief Driver for Reset & Clock Control of STM32F4X family processor. - * - * Based on reference manual: - * RM0368 Reference manual STM32F401xB/C and STM32F401xD/E - * advanced ARM ® -based 32-bit MCUs - * - * Chapter 6. Reset and Clock control (RCC) for STM43F401xB/C and STM32F401xD/E - */ - -/* 6.3.1 Clock control register (RCC_CR) */ -enum { - STM32F4X_RCC_CFG_PLL_SRC_HSI = 0x0, - STM32F4X_RCC_CFG_PLL_SRC_HSE = 0x1, -}; - -enum { - STM32F4X_RCC_CFG_SYSCLK_SRC_HSI = 0x0, - STM32F4X_RCC_CFG_SYSCLK_SRC_HSE = 0x1, - STM32F4X_RCC_CFG_SYSCLK_SRC_PLL = 0x2, -}; - -enum { - STM32F4X_RCC_CFG_PLLP_DIV_2 = 0x0, - STM32F4X_RCC_CFG_PLLP_DIV_4 = 0x1, - STM32F4X_RCC_CFG_PLLP_DIV_6 = 0x2, - STM32F4X_RCC_CFG_PLLP_DIV_8 = 0x3, -}; - -enum { - STM32F4X_RCC_CFG_HCLK_DIV_0 = 0x0, - STM32F4X_RCC_CFG_HCLK_DIV_2 = 0x4, - STM32F4X_RCC_CFG_HCLK_DIV_4 = 0x5, - STM32F4X_RCC_CFG_HCLK_DIV_8 = 0x6, - STM32F4X_RCC_CFG_HCLK_DIV_16 = 0x7, -}; - -enum { - STM32F4X_RCC_CFG_SYSCLK_DIV_0 = 0x0, - STM32F4X_RCC_CFG_SYSCLK_DIV_2 = 0x8, - STM32F4X_RCC_CFG_SYSCLK_DIV_4 = 0x9, - STM32F4X_RCC_CFG_SYSCLK_DIV_8 = 0xa, - STM32F4X_RCC_CFG_SYSCLK_DIV_16 = 0xb, - STM32F4X_RCC_CFG_SYSCLK_DIV_64 = 0xc, - STM32F4X_RCC_CFG_SYSCLK_DIV_128 = 0xd, - STM32F4X_RCC_CFG_SYSCLK_DIV_256 = 0xe, - STM32F4X_RCC_CFG_SYSCLK_DIV_512 = 0xf, -}; - -/** - * @brief Reset and Clock Control - */ - -/* Helpers */ -enum { - STM32F4X_RCC_APB1ENR_PWREN = 0x10000000U, -}; - -union __rcc_cr { - u32_t val; - struct { - u32_t hsion :1 __packed; - u32_t hsirdy :1 __packed; - u32_t rsvd__2 :1 __packed; - u32_t hsitrim :5 __packed; - u32_t hsical :8 __packed; - u32_t hseon :1 __packed; - u32_t hserdy :1 __packed; - u32_t hsebyp :1 __packed; - u32_t csson :1 __packed; - u32_t rsvd__20_23 :4 __packed; - u32_t pllon :1 __packed; - u32_t pllrdy :1 __packed; - u32_t plli2son :1 __packed; - u32_t plli2srdy :1 __packed; - u32_t pllsaion :1 __packed; - u32_t pllsairdy :1 __packed; - u32_t rsvd__30_31 :2 __packed; - } bit; -}; - -union __rcc_pllcfgr { - u32_t val; - struct { - u32_t pllm :6 __packed; - u32_t plln :9 __packed; - u32_t rsvd__15 :1 __packed; - u32_t pllp :2 __packed; - u32_t rsvd__18_21 :4 __packed; - u32_t pllsrc :1 __packed; - u32_t rsvd__23 :1 __packed; - u32_t pllq :4 __packed; - u32_t rsvd__28_31 :4 __packed; - } bit; -}; - -union __rcc_cfgr { - u32_t val; - struct { - u32_t sw :2 __packed; - u32_t sws :2 __packed; - u32_t hpre :4 __packed; - u32_t rsvd__8_9 :2 __packed; - u32_t ppre1 :3 __packed; - u32_t ppre2 :3 __packed; - u32_t rtcpre :5 __packed; - u32_t mco1 :2 __packed; - u32_t i2sscr :1 __packed; - u32_t mco1pre :3 __packed; - u32_t mco2pre :3 __packed; - u32_t mco2 :2 __packed; - } bit; -}; - -struct stm32f4x_rcc { - union __rcc_cr cr; - union __rcc_pllcfgr pllcfgr; - union __rcc_cfgr cfgr; - u32_t cir; - u32_t ahb1rstr; - u32_t ahb2rstr; - u32_t ahb3rstr; - u32_t rsvd0; - u32_t apb1rstr; - u32_t apb2rstr; - u32_t rsvd1[2]; - u32_t ahb1enr; - u32_t ahb2enr; - u32_t ahb3enr; - u32_t rsvd2; - u32_t apb1enr; - u32_t apb2enr; - u32_t rsvd3[2]; - u32_t ahb1lpenr; - u32_t ahb2lpenr; - u32_t ahb3lpenr; - u32_t rsvd4; - u32_t apb1lpenr; - u32_t apb2lpenr; - u32_t rsvd5[2]; - u32_t bdcr; - u32_t csr; - u32_t rsvd6[2]; - u32_t sscgr; - u32_t plli2scfgr; - u32_t rsvd7; - u32_t dckcfgr; -}; - -#endif /* _STM32F4X_CLOCK_H_ */ diff --git a/arch/arm/soc/st_stm32/stm32f4/soc.c b/arch/arm/soc/st_stm32/stm32f4/soc.c index f1e4d693a..e2e27cee9 100644 --- a/arch/arm/soc/st_stm32/stm32f4/soc.c +++ b/arch/arm/soc/st_stm32/stm32f4/soc.c @@ -53,8 +53,14 @@ static int st_stm32f4_init(struct device *arg) irq_unlock(key); +#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE + /* Update CMSIS SystemCoreClock variable (HCLK) */ + /* At reset, System core clock is set to 4MHz */ + SystemCoreClock = 4000000; +#else /* Update CMSIS SystemCoreClock variable (HCLK) */ SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; +#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ return 0; } diff --git a/arch/arm/soc/st_stm32/stm32f4/soc.h b/arch/arm/soc/st_stm32/stm32f4/soc.h index 372d2afcf..d611d1b07 100644 --- a/arch/arm/soc/st_stm32/stm32f4/soc.h +++ b/arch/arm/soc/st_stm32/stm32f4/soc.h @@ -52,6 +52,13 @@ enum stm32f4x_pin_config_mode { #include "soc_irq.h" +#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE +#include <stm32f4xx_ll_utils.h> +#include <stm32f4xx_ll_bus.h> +#include <stm32f4xx_ll_rcc.h> +#include <stm32f4xx_ll_system.h> +#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ + #endif /* !_ASMLANGUAGE */ #endif /* _STM32F4_SOC_H_ */ diff --git a/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c b/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c index 388be1512..8a0bd865b 100644 --- a/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c +++ b/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c @@ -234,9 +234,9 @@ int stm32_gpio_enable_int(int port, int pin) (struct stm32f4x_syscfg *)SYSCFG_BASE; volatile union syscfg_exticr *exticr; struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME); - struct stm32f4x_pclken pclken = { - .bus = STM32F4X_CLOCK_BUS_APB2, - .enr = STM32F4X_CLOCK_ENABLE_SYSCFG + struct stm32_pclken pclken = { + .bus = STM32_CLOCK_BUS_APB2, + .enr = LL_APB2_GRP1_PERIPH_SYSCFG }; int shift = 0; diff --git a/arch/arm/soc/st_stm32/stm32f4/soc_registers.h b/arch/arm/soc/st_stm32/stm32f4/soc_registers.h index 1ad979890..c7a2d5cb7 100644 --- a/arch/arm/soc/st_stm32/stm32f4/soc_registers.h +++ b/arch/arm/soc/st_stm32/stm32f4/soc_registers.h @@ -8,7 +8,6 @@ #define _STM32F4_SOC_REGISTERS_H_ /* include register mapping headers */ -#include "rcc_registers.h" #include "flash_registers.h" #include "gpio_registers.h" diff --git a/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg b/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg new file mode 100644 index 000000000..c4b9b1a88 --- /dev/null +++ b/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg @@ -0,0 +1,18 @@ +# Kconfig - ST Microelectronics STM32L475xG MCU +# +# Copyright (c) 2017 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_STM32L475XG + +config SOC + string + default stm32l475xx + +config NUM_IRQS + int + default 82 + +endif # SOC_STM32L475XG diff --git a/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc b/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc index dd1127580..69f80ebc2 100644 --- a/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc +++ b/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc @@ -14,4 +14,8 @@ config SOC_STM32L476XX bool "STM32L476XX" select HAS_STM32CUBE +config SOC_STM32L475XG + bool "STM32L475XG" + select HAS_STM32CUBE + endchoice diff --git a/arch/arm/soc/ti_lm3s6965/Kconfig.defconfig b/arch/arm/soc/ti_lm3s6965/Kconfig.defconfig index a7d0e0089..0ccddbcce 100644 --- a/arch/arm/soc/ti_lm3s6965/Kconfig.defconfig +++ b/arch/arm/soc/ti_lm3s6965/Kconfig.defconfig @@ -11,16 +11,6 @@ if SOC_TI_LM3S6965 config SOC default ti_lm3s6965 -config SRAM_BASE_ADDRESS - default 0x20000000 - -config FLASH_BASE_ADDRESS - default 0x00000000 - -config NUM_IRQ_PRIO_BITS - int - default 3 - config NUM_IRQS int # must be >= the highest interrupt number used @@ -36,31 +26,11 @@ if UART_STELLARIS config UART_STELLARIS_PORT_0 def_bool y -if UART_STELLARIS_PORT_0 -config UART_STELLARIS_PORT_0_IRQ_PRI - default 3 -config UART_STELLARIS_PORT_0_BAUD_RATE - default 115200 -endif - config UART_STELLARIS_PORT_1 def_bool y -if UART_STELLARIS_PORT_1 -config UART_STELLARIS_PORT_1_IRQ_PRI - default 3 -config UART_STELLARIS_PORT_1_BAUD_RATE - default 115200 -endif - config UART_STELLARIS_PORT_2 def_bool y -if UART_STELLARIS_PORT_2 -config UART_STELLARIS_PORT_2_IRQ_PRI - default 3 -config UART_STELLARIS_PORT_2_BAUD_RATE - default 115200 -endif endif # UART_STELLARIS diff --git a/arch/arm/soc/ti_lm3s6965/Makefile b/arch/arm/soc/ti_lm3s6965/Makefile index cce05751d..b086b674c 100644 --- a/arch/arm/soc/ti_lm3s6965/Makefile +++ b/arch/arm/soc/ti_lm3s6965/Makefile @@ -1,3 +1,2 @@ obj-y += soc_config.o obj-y += soc.o -obj-y += scp.o diff --git a/arch/arm/soc/ti_lm3s6965/scp.c b/arch/arm/soc/ti_lm3s6965/scp.c deleted file mode 100644 index 73c7aba9b..000000000 --- a/arch/arm/soc/ti_lm3s6965/scp.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2013-2014 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief TI LM3S6965 System Control Peripherals interface - * - * - * Library for controlling target-specific devices present in the 0x400fe000 - * peripherals memory region. - * - * Currently, only enabling the main OSC with default value is implemented. - */ - -#include <zephyr/types.h> -#include <toolchain.h> -#include <sections.h> - -#include "scp.h" - -/* System Control Peripheral (SCP) Registers */ - -volatile struct __scp __scp_section __scp; - -/** - * - * @brief Enable main oscillator with default frequency of 6MHz - * - * @return N/A - */ -void _ScpMainOscEnable(void) -{ - union __rcc reg; - - reg.value = __scp.clock.rcc.value; - reg.bit.moscdis = 0; - reg.bit.oscsrc = _SCP_OSC_SOURCE_MAIN; - reg.bit.xtal = _SCP_CRYSTAL_6MHZ; - - __scp.clock.rcc.value = reg.value; -} diff --git a/arch/arm/soc/ti_lm3s6965/scp.h b/arch/arm/soc/ti_lm3s6965/scp.h deleted file mode 100644 index cbee6a74e..000000000 --- a/arch/arm/soc/ti_lm3s6965/scp.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2013-2014 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief TI LM3S6965 System Control Peripherals interface - * - * This module defines the System Control Peripheral Registers for TI LM3S6965 - * processor. The registers defined are in region 0x400fe000. - * - * System Control 0x400fe000 - * - * These modules are not defined: - * - * Hibernation Module 0x400fc000 - * Internal Memory 0x400fd000 - * Hibernation Module 0x400fc000 - * - * The registers and bit field names are taken from the 'Stellaris LM3S6965 - * Microcontroller DATA SHEET (DS-LM3S6965-12746.2515) revision H' document, - * section 5.4/5.5, pp .184-200. - */ - -#ifndef _SCP_H_ -#define _SCP_H_ - -#include <zephyr/types.h> - -#ifdef __cplusplus -extern "C" { -#endif - -#define _SCP_OSC_SOURCE_MAIN 0 -#define _SCP_OSC_SOURCE_INTERNAL 1 -#define _SCP_OSC_SOURCE_INTERNAL_DIV4 2 -#define _SCP_OSC_SOURCE_INTERNAL_20KHZ 3 -#define _SCP_OSC_SOURCE_EXTERNAL_32KHZ 7 /* Valid with RCC2 only */ - -#define _SCP_CRYSTAL_1MHZ_NOPLL 0 -#define _SCP_CRYSTAL_1_8432MHZ_NOPLL 1 -#define _SCP_CRYSTAL_2MHZ_NOPLL 2 -#define _SCP_CRYSTAL_2_4576MHZ_NOPLL 3 -#define _SCP_CRYSTAL_3_579545MHZ 4 -#define _SCP_CRYSTAL_3_6864MHZ 5 -#define _SCP_CRYSTAL_4MHZ 6 -#define _SCP_CRYSTAL_4_0964MHZ 7 -#define _SCP_CRYSTAL_4_9152MHZ 8 -#define _SCP_CRYSTAL_5MHZ 9 -#define _SCP_CRYSTAL_5_12MHZ 10 -#define _SCP_CRYSTAL_6MHZ 11 /* reset value */ -#define _SCP_CRYSTAL_6_144MHZ 12 -#define _SCP_CRYSTAL_7_3728MHZ 13 -#define _SCP_CRYSTAL_8MHZ 14 -#define _SCP_CRYSTAL_8_192MHZ 15 - -union __rcc { - u32_t value; - struct { - u32_t moscdis : 1 __packed; - u32_t ioscdis : 1 __packed; - u32_t rsvd__2_3 : 2 __packed; - u32_t oscsrc : 2 __packed; - u32_t xtal : 4 __packed; - u32_t rsvd__10 : 1 __packed; - u32_t bypass : 1 __packed; - u32_t rsvd__12 : 1 __packed; - u32_t pwrdn : 1 __packed; - u32_t rsvd__14_16 : 3 __packed; - u32_t pwmdiv : 3 __packed; /* 2**(n+1) */ - u32_t usepwmdiv : 1 __packed; - u32_t rsvd__21 : 1 __packed; - u32_t usesysdiv : 1 __packed; - u32_t sysdiv : 4 __packed; - u32_t acg : 1 __packed; - u32_t rsvd__28_31 : 4 __packed; - } bit; -}; - -union __rcc2 { - u32_t value; - struct { - u8_t rsvd__0_3 : 4 __packed; - u8_t oscsrc2 : 3 __packed; - u16_t rsvd__7_10 : 4 __packed; - u8_t bypass2 : 1 __packed; - u8_t rsvd__12 : 1 __packed; - u8_t pwrdn2 : 1 __packed; - u16_t rsvd__14_22 : 9 __packed; - u16_t sysdiv2 : 6 __packed; - u8_t rsvd__29_30 : 2 __packed; - u8_t usercc2 : 1 __packed; - } bit; -}; - -struct __scp { - u32_t did0; /* 0x000 RO Device ID*/ - u32_t did1; /* 0x004 RO Device ID*/ - u32_t dc0; /* 0x008 RO Device Capabilities */ - u32_t dc1; /* 0x00c RO Device Capabilities */ - u32_t dc2; /* 0x010 RO Device Capabilities */ - u32_t dc3; /* 0x014 RO Device Capabilities */ - u32_t dc4; /* 0x018 RO Device capabilities */ - - u32_t rsvd__01c_02f[(0x30 - 0x1c) / 4]; - - u32_t pborctl; /* 0x030 RW Brown-Out Reset ConTroL */ - u32_t ldopctl; /* 0x034 RW LDO Power ConTroL */ - - u32_t rsvd__038_03f[(0x40 - 0x38) / 4]; - - u32_t srcr0; /* 0x040 RW Software Reset Control Register */ - u32_t srcr1; /* 0x044 RW Software Reset Control Register */ - u32_t srcr2; /* 0x048 RW Software Reset Control Register */ - - u32_t rsvd__04c_04f; - - u32_t ris; /* 0x050 RO Raw Interrupt Status */ - u32_t imc; /* 0x054 RW Interrupt Mask Control */ - u32_t misc; /* 0x058 RW1C Masked Int. Status & Clear */ - u32_t resc; /* 0x05C RW RESet Cause */ - struct { - union __rcc rcc; /* 0x060 RW Run-mode Clock Configuration */ - u32_t pllcfg; /* 0x064 RW xtal-to-pll translation */ - - u32_t rsvd__068_06f[(0x70 - 0x068) / 4]; - - union __rcc2 rcc2; /* 0x070 RW Run-mode Clock Configuration */ - - u32_t rsvd__074_0ff[(0x100 - 0x074) / 4]; - - u32_t rcgc0; /* 0x100 RW Run-mode Clock Gating */ - u32_t rcgc1; /* 0x104 RW Run-mode Clock Gating */ - u32_t rcgc2; /* 0x108 RW Run-mode Clock Gating */ - - u32_t rsvd__10c_10f; - - u32_t scgc0; /* 0x110 RW Sleep-mode Clock Gating */ - u32_t scgc1; /* 0x114 RW Sleep-mode Clock Gating */ - u32_t scgc2; /* 0x118 RW Sleep-mode Clock Gating */ - - u32_t rsvd__11c_11f; - - u32_t dcgc0; /* 0x120 RW Deep sleep mode Clock Gating */ - u32_t dcgc1; /* 0x124 RW Deep sleep mode Clock Gating */ - u32_t dcgc2; /* 0x128 RW Deep sleep mode Clock Gating */ - - u32_t rsvd__12c_143[(0x144 - 0x12c) / 4]; - - u32_t - dslpclkcfg; /* 0x144 RW Deep SLeeP CLocK ConFiGuration - */ - } clock; -}; - -extern volatile struct __scp __scp; - -#ifdef __cplusplus -} -#endif - -#endif /* _SCP_H_ */ diff --git a/arch/arm/soc/ti_lm3s6965/soc.h b/arch/arm/soc/ti_lm3s6965/soc.h index 6ae548ca6..56509edf2 100644 --- a/arch/arm/soc/ti_lm3s6965/soc.h +++ b/arch/arm/soc/ti_lm3s6965/soc.h @@ -32,8 +32,6 @@ extern "C" { #define IRQ_GPIO_PORTC 2 #define IRQ_GPIO_PORTD 3 #define IRQ_GPIO_PORTE 4 -#define IRQ_UART0 5 -#define IRQ_UART1 6 #define IRQ_SSI0 7 #define IRQ_I2C0 8 #define IRQ_PWM_FAULT 9 @@ -60,7 +58,6 @@ extern "C" { #define IRQ_GPIO_PORTF 30 #define IRQ_GPIO_PORTG 31 #define IRQ_RESERVED1 32 -#define IRQ_UART2 33 #define IRQ_RESERVED2 34 #define IRQ_TIMER3A 35 #define IRQ_TIMER3B 36 @@ -83,15 +80,6 @@ extern "C" { #define UART_IRQ_FLAGS 0 -#define UART_STELLARIS_PORT_0_BASE_ADDR 0x4000C000 -#define UART_STELLARIS_PORT_0_IRQ IRQ_UART0 - -#define UART_STELLARIS_PORT_1_BASE_ADDR 0x4000D000 -#define UART_STELLARIS_PORT_1_IRQ IRQ_UART1 - -#define UART_STELLARIS_PORT_2_BASE_ADDR 0x4000E000 -#define UART_STELLARIS_PORT_2_IRQ IRQ_UART2 - #define UART_STELLARIS_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ #endif /* CONFIG_UART_STELLARIS */ diff --git a/arch/arm/soc/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf b/arch/arm/soc/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf new file mode 100644 index 000000000..34c1de3b9 --- /dev/null +++ b/arch/arm/soc/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf @@ -0,0 +1,43 @@ +# Kconfig.defconfig.cc3220sf - TI SimpleLink CC3220SF SoC +# + +if SOC_CC3220SF + +config SOC + string + default cc3220sf + +config NUM_IRQS + int + # must be >= the highest interrupt number used + # This includes the NWP interrupt + default 179 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 80000000 + +config TEXT_SECTION_OFFSET + default 0x800 if XIP + default 0x0 if !XIP + +if GPIO + +config GPIO_CC32XX + def_bool y + +config GPIO_CC32XX_A0 + default n + +config GPIO_CC32XX_A1 + default y + +config GPIO_CC32XX_A2 + default y + +config GPIO_CC32XX_A3 + default n + +endif # GPIO + +endif # SOC_CC3220SF diff --git a/arch/arm/soc/ti_simplelink/cc32xx/Kconfig.soc b/arch/arm/soc/ti_simplelink/cc32xx/Kconfig.soc index 6424fd622..c97ea90a5 100644 --- a/arch/arm/soc/ti_simplelink/cc32xx/Kconfig.soc +++ b/arch/arm/soc/ti_simplelink/cc32xx/Kconfig.soc @@ -9,4 +9,19 @@ config SOC_CC3200 bool "CC3200" select HAS_CC3200SDK +config SOC_CC3220SF + bool "CC3220SF" + select HAS_CC3220SDK + endchoice + + +if SOC_CC3220SF + +config CC3220SF_DEBUG + bool "Prepend debug header, disabling flash verification" + depends on XIP + default y if XIP + default n if !XIP + +endif # SOC_CC3220SF diff --git a/arch/arm/soc/ti_simplelink/cc32xx/README b/arch/arm/soc/ti_simplelink/cc32xx/README index 70ef78235..f5a6f2938 100644 --- a/arch/arm/soc/ti_simplelink/cc32xx/README +++ b/arch/arm/soc/ti_simplelink/cc32xx/README @@ -2,9 +2,17 @@ CC3200 Board and Bootloader info taken from: * http://www.ti.com.cn/cn/lit/ug/swru367c/swru367c.pdf * http://www.ti.com/lit/ug/swru369c/swru369c.pdf -Notes: +CC3220 Info taken from: +* http://www.ti.com/lit/ug/swru465/swru465.pdf + +Notes for CC3200: * CC3200 has no integrated flash Memory. * TI bootloader takes first 16Kb of the 256Kb SRAM, so app must start at 0x20004000. CC3200 Kconfig must set SRAM size to 240Kb or less, since Zephyr computes TOP_OF_MEMORY (used for stack) based on SRAM_BASE_ADDRESS + SRAM_SIZE. + +Notes for CC3220SF: + * Text must start at 0x800 offset in flash. The first 0x800 bytes are + reserved for the flash header. + * See CONFIG_TEXT_SECTION_OFFSET. diff --git a/arch/arm/soc/ti_simplelink/cc32xx/soc.c b/arch/arm/soc/ti_simplelink/cc32xx/soc.c index 61ac3bd1f..ffa424182 100644 --- a/arch/arm/soc/ti_simplelink/cc32xx/soc.c +++ b/arch/arm/soc/ti_simplelink/cc32xx/soc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, Texas Instruments Incorporated + * Copyright (c) 2016-2017, Texas Instruments Incorporated * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,7 +12,7 @@ #include <driverlib/rom_map.h> #include <driverlib/prcm.h> -static int ti_cc3200_init(struct device *arg) +static int ti_cc32xx_init(struct device *arg) { ARG_UNUSED(arg); @@ -30,4 +30,4 @@ static int ti_cc3200_init(struct device *arg) return 0; } -SYS_INIT(ti_cc3200_init, PRE_KERNEL_1, 0); +SYS_INIT(ti_cc32xx_init, PRE_KERNEL_1, 0); |