diff options
| author | Damien George <damien.p.george@gmail.com> | 2017-10-17 16:31:12 +1100 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2017-10-17 16:31:12 +1100 |
| commit | 285ac585322f0ffced76d25a6f19cd1fa30b3514 (patch) | |
| tree | 76ee755edef8e4332ec6f6d6a455c52a34dd9836 | |
| parent | d90ade5e3e62b28c1f04d18f206509a488d62ec0 (diff) | |
stm32/modnwwiznet5k: Increase SPI bus speed to 42MHz.
The W5200 and W5500 can support up to 80MHz so 42MHz (the maximum the
pyboard can do in its standard configuration) should be safe.
Tested to give around 1050000 kbytes/sec TCP download speed on a W5500,
which is about 10% more than with the previous SPI speed of 21MHz.
| -rw-r--r-- | ports/stm32/modnwwiznet5k.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ports/stm32/modnwwiznet5k.c b/ports/stm32/modnwwiznet5k.c index d59125054..717d88b39 100644 --- a/ports/stm32/modnwwiznet5k.c +++ b/ports/stm32/modnwwiznet5k.c @@ -346,7 +346,7 @@ STATIC mp_obj_t wiznet5k_make_new(const mp_obj_type_t *type, size_t n_args, size wiznet5k_obj.spi->Init.CLKPolarity = SPI_POLARITY_LOW; // clock is low when idle wiznet5k_obj.spi->Init.CLKPhase = SPI_PHASE_1EDGE; // data latched on first edge, which is rising edge for low-idle wiznet5k_obj.spi->Init.NSS = SPI_NSS_SOFT; - wiznet5k_obj.spi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4; // clock freq = f_PCLK / this_prescale_value; Wiz820i can do up to 80MHz + wiznet5k_obj.spi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; // clock freq = f_PCLK / this_prescale_value; Wiz820i can do up to 80MHz wiznet5k_obj.spi->Init.FirstBit = SPI_FIRSTBIT_MSB; wiznet5k_obj.spi->Init.TIMode = SPI_TIMODE_DISABLED; wiznet5k_obj.spi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; |