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authoriveresov <none@none>2014-01-21 20:05:28 -0800
committeriveresov <none@none>2014-01-21 20:05:28 -0800
commit0ddbeded50e9bfd409fb25a334e7a9167b5af3b9 (patch)
tree00e5b9169dbb778a877b67ea46147a149d3bb784
parent82b9e7a14faf722cff81da06e3d489f16780b0b5 (diff)
8031743: C2: loadI2L_immI broken for negative memory values
Summary: Restrict loadI2L_imm optimizations to positive values of mask Reviewed-by: kvn, dlong
-rw-r--r--src/cpu/sparc/vm/sparc.ad29
-rw-r--r--src/cpu/x86/vm/x86_32.ad17
-rw-r--r--src/cpu/x86/vm/x86_64.ad17
-rw-r--r--test/compiler/codegen/LoadWithMask2.java55
4 files changed, 103 insertions, 15 deletions
diff --git a/src/cpu/sparc/vm/sparc.ad b/src/cpu/sparc/vm/sparc.ad
index bc67291b9..1b7752542 100644
--- a/src/cpu/sparc/vm/sparc.ad
+++ b/src/cpu/sparc/vm/sparc.ad
@@ -3355,8 +3355,8 @@ operand immI16() %{
interface(CONST_INTER);
%}
-// Unsigned (positive) Integer Immediate: 13-bit
-operand immU13() %{
+// Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
+operand immU12() %{
predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
match(ConI);
op_cost(0);
@@ -3392,6 +3392,17 @@ operand immI5() %{
interface(CONST_INTER);
%}
+// Int Immediate non-negative
+operand immU31()
+%{
+ predicate(n->get_int() >= 0);
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
// Integer Immediate: 0-bit
operand immI0() %{
predicate(n->get_int() == 0);
@@ -5841,13 +5852,13 @@ instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
ins_pipe(iload_mem);
%}
-// Load Integer with a 13-bit mask into a Long Register
-instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
+// Load Integer with a 12-bit mask into a Long Register
+instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
ins_cost(MEMORY_REF_COST + DEFAULT_COST);
size(2*4);
- format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
+ format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
"AND $dst,$mask,$dst" %}
ins_encode %{
Register Rdst = $dst$$Register;
@@ -5857,13 +5868,13 @@ instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
ins_pipe(iload_mem);
%}
-// Load Integer with a 32-bit mask into a Long Register
-instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
+// Load Integer with a 31-bit mask into a Long Register
+instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
effect(TEMP dst, TEMP tmp);
ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
- format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
+ format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
"SET $mask,$tmp\n\t"
"AND $dst,$tmp,$dst" %}
ins_encode %{
@@ -8958,7 +8969,7 @@ instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
ins_pipe(ialu_cconly_reg_reg);
%}
-instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
+instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
match(Set icc (CmpU op1 op2));
size(4);
diff --git a/src/cpu/x86/vm/x86_32.ad b/src/cpu/x86/vm/x86_32.ad
index 2aa9e5f57..90c1d899f 100644
--- a/src/cpu/x86/vm/x86_32.ad
+++ b/src/cpu/x86/vm/x86_32.ad
@@ -3889,6 +3889,17 @@ operand immI16() %{
interface(CONST_INTER);
%}
+// Int Immediate non-negative
+operand immU31()
+%{
+ predicate(n->get_int() >= 0);
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
// Constant for long shifts
operand immI_32() %{
predicate( n->get_int() == 32 );
@@ -6119,12 +6130,12 @@ instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr
ins_pipe(ialu_reg_mem);
%}
-// Load Integer with 32-bit mask into Long Register
-instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
+// Load Integer with 31-bit mask into Long Register
+instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
effect(KILL cr);
- format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
+ format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
"XOR $dst.hi,$dst.hi\n\t"
"AND $dst.lo,$mask" %}
ins_encode %{
diff --git a/src/cpu/x86/vm/x86_64.ad b/src/cpu/x86/vm/x86_64.ad
index 182a7012a..9fe92953a 100644
--- a/src/cpu/x86/vm/x86_64.ad
+++ b/src/cpu/x86/vm/x86_64.ad
@@ -3086,6 +3086,17 @@ operand immI16()
interface(CONST_INTER);
%}
+// Int Immediate non-negative
+operand immU31()
+%{
+ predicate(n->get_int() >= 0);
+ match(ConI);
+
+ op_cost(0);
+ format %{ %}
+ interface(CONST_INTER);
+%}
+
// Constant for long shifts
operand immI_32()
%{
@@ -5042,12 +5053,12 @@ instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
ins_pipe(ialu_reg_mem);
%}
-// Load Integer with a 32-bit mask into Long Register
-instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
+// Load Integer with a 31-bit mask into Long Register
+instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
effect(KILL cr);
- format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
+ format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
"andl $dst, $mask" %}
ins_encode %{
Register Rdst = $dst$$Register;
diff --git a/test/compiler/codegen/LoadWithMask2.java b/test/compiler/codegen/LoadWithMask2.java
new file mode 100644
index 000000000..c1ae52881
--- /dev/null
+++ b/test/compiler/codegen/LoadWithMask2.java
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2014, Oracle and/or its affiliates. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ */
+
+/*
+ * @test
+ * @bug 8031743
+ * @summary loadI2L_immI broken for negative memory values
+ * @run main/othervm -server -Xbatch -XX:-TieredCompilation -XX:CompileCommand=compileonly,*.foo* LoadWithMask2
+ *
+ */
+public class LoadWithMask2 {
+ static int x;
+ static long foo1() {
+ return x & 0xfffffffe;
+ }
+ static long foo2() {
+ return x & 0xff000000;
+ }
+ static long foo3() {
+ return x & 0x8abcdef1;
+ }
+
+ public static void main(String[] args) {
+ x = -1;
+ long l = 0;
+ for (int i = 0; i < 100000; ++i) {
+ l = foo1() & foo2() & foo3();
+ }
+ if (l > 0) {
+ System.out.println("FAILED");
+ System.exit(97);
+ }
+ System.out.println("PASSED");
+ }
+}