blob: 62ebff922aaee9ec268834924801f91207dba492 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
|
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __AM335XSDIO_H__
#define __AM335XSDIO_H__
//MMC/SD/SDIO1 register definitions.
#define MMCHS1BASE 0x48060100
#define MMC_REFERENCE_CLK (48000000) // 48 MHz
#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
#define SOFTRESET BIT1
#define ENAWAKEUP BIT2
#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
#define RESETDONE_MASK BIT0
#define RESETDONE BIT0
#define MMCHS_CSRE (MMCHS1BASE + 0x24)
#define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
#define MMCHS_CON (MMCHS1BASE + 0x2C)
#define OD BIT0
#define NOINIT (0x0UL << 1)
#define INIT BIT1
#define HR BIT2
#define STR BIT3
#define MODE BIT4
#define DW8_1_4_BIT (0x0UL << 5)
#define DW8_8_BIT BIT5
#define MIT BIT6
#define CDP BIT7
#define WPP BIT8
#define CTPL BIT11
#define CEATA_OFF (0x0UL << 12)
#define CEATA_ON BIT12
#define MMCHS_PWCNT (MMCHS1BASE + 0x30)
#define MMCHS_BLK (MMCHS1BASE + 0x104)
#define BLEN_512BYTES (0x200UL << 0)
#define MMCHS_ARG (MMCHS1BASE + 0x108)
#define MMCHS_CMD (MMCHS1BASE + 0x10C)
#define DE_ENABLE BIT0
#define BCE_ENABLE BIT1
#define ACEN_ENABLE BIT2
#define DDIR_READ BIT4
#define DDIR_WRITE (0x0UL << 4)
#define MSBS_SGLEBLK (0x0UL << 5)
#define MSBS_MULTBLK BIT5
#define RSP_TYPE_MASK (0x3UL << 16)
#define RSP_TYPE_136BITS BIT16
#define RSP_TYPE_48BITS (0x2UL << 16)
#define CCCE_ENABLE BIT19
#define CICE_ENABLE BIT20
#define DP_ENABLE BIT21
#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
#define MMCHS_RSP10 (MMCHS1BASE + 0x110)
#define MMCHS_RSP32 (MMCHS1BASE + 0x114)
#define MMCHS_RSP54 (MMCHS1BASE + 0x118)
#define MMCHS_RSP76 (MMCHS1BASE + 0x11C)
#define MMCHS_DATA (MMCHS1BASE + 0x120)
#define MMCHS_PSTATE (MMCHS1BASE + 0x124)
#define CMDI_MASK BIT0
#define CMDI_ALLOWED (0x0UL << 0)
#define CMDI_NOT_ALLOWED BIT0
#define DATI_MASK BIT1
#define DATI_ALLOWED (0x0UL << 1)
#define DATI_NOT_ALLOWED BIT1
#define MMCHS_HCTL (MMCHS1BASE + 0x128)
#define DTW_1_BIT (0x0UL << 1)
#define DTW_4_BIT BIT1
#define SDBP_MASK BIT8
#define SDBP_OFF (0x0UL << 8)
#define SDBP_ON BIT8
#define SDVS_1_8_V (0x5UL << 9)
#define SDVS_3_0_V (0x6UL << 9)
#define IWE BIT24
#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
#define ICE BIT0
#define ICS_MASK BIT1
#define ICS BIT1
#define CEN BIT2
#define CLKD_MASK (0x3FFUL << 6)
#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
#define CLKD_400KHZ (0xF0UL)
#define DTO_MASK (0xFUL << 16)
#define DTO_VAL (0xEUL << 16)
#define SRA BIT24
#define SRC_MASK BIT25
#define SRC BIT25
#define SRD BIT26
#define MMCHS_STAT (MMCHS1BASE + 0x130)
#define CC BIT0
#define TC BIT1
#define BWR BIT4
#define BRR BIT5
#define ERRI BIT15
#define CTO BIT16
#define DTO BIT20
#define DCRC BIT21
#define DEB BIT22
#define MMCHS_IE (MMCHS1BASE + 0x134)
#define CC_EN BIT0
#define TC_EN BIT1
#define BWR_EN BIT4
#define BRR_EN BIT5
#define CTO_EN BIT16
#define CCRC_EN BIT17
#define CEB_EN BIT18
#define CIE_EN BIT19
#define DTO_EN BIT20
#define DCRC_EN BIT21
#define DEB_EN BIT22
#define CERR_EN BIT28
#define BADA_EN BIT29
#define MMCHS_ISE (MMCHS1BASE + 0x138)
#define CC_SIGEN BIT0
#define TC_SIGEN BIT1
#define BWR_SIGEN BIT4
#define BRR_SIGEN BIT5
#define CTO_SIGEN BIT16
#define CCRC_SIGEN BIT17
#define CEB_SIGEN BIT18
#define CIE_SIGEN BIT19
#define DTO_SIGEN BIT20
#define DCRC_SIGEN BIT21
#define DEB_SIGEN BIT22
#define CERR_SIGEN BIT28
#define BADA_SIGEN BIT29
#define MMCHS_AC12 (MMCHS1BASE + 0x13C)
#define MMCHS_CAPA (MMCHS1BASE + 0x140)
#define VS30 BIT25
#define VS18 BIT26
#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
#define MMCHS_REV (MMCHS1BASE + 0x1FC)
#define CMD0 INDX(0)
#define CMD0_INT_EN (CC_EN | CEB_EN)
#define CMD1 (INDX(1) | RSP_TYPE_48BITS)
#define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN)
#define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS)
#define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD5 (INDX(5) | RSP_TYPE_48BITS)
#define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN)
#define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
#define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ)
#define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
#define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD25 (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
#define CMD25_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define ACMD41 (INDX(41) | RSP_TYPE_48BITS)
#define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#define ACMD6 (INDX(6) | RSP_TYPE_48BITS)
#define ACMD6_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
#endif //__AM335XSDIO_H__
|
