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Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8996.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8996.dtsi233
1 files changed, 227 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 3787d85272ae..e6791ecda6a8 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -10,6 +10,7 @@
* GNU General Public License for more details.
*/
+#include <dt-bindings/interconnect/qcom.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
@@ -38,18 +39,19 @@
#size-cells = <2>;
ranges;
- mba_region: mba@91500000 {
- reg = <0x0 0x91500000 0x0 0x200000>;
+ mba_region: mba@91600000 {
+ reg = <0x0 0x91600000 0x0 0x200000>;
no-map;
};
- slpi_region: slpi@90b00000 {
- reg = <0x0 0x90b00000 0x0 0xa00000>;
+ slpi_region: slpi@90c00000 {
+ reg = <0x0 0x90c00000 0x0 0xa00000>;
no-map;
};
venus_region: venus@90400000 {
- reg = <0x0 0x90400000 0x0 0x700000>;
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x90400000 0x0 0x800000>;
no-map;
};
@@ -91,7 +93,7 @@
zap_shader_region: gpu@8f200000 {
compatible = "shared-dma-pool";
- reg = <0 0x8f200000 0 0x2300000>;
+ reg = <0 0x8f200000 0 0x100000>;
no-map;
};
};
@@ -575,6 +577,10 @@
#clock-cells = <1>;
};
+ interconnect-smd-rpm {
+ compatible = "qcom,interconnect-smd-rpm";
+ };
+
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
@@ -721,6 +727,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c0_default>;
pinctrl-1 = <&blsp2_i2c0_sleep>;
+ interconnects = <&pnoc 84 &bimc 512>;
+ interconnect-names = "ddr";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -752,6 +760,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
+ interconnects = <&pnoc 84 &bimc 512>;
+ interconnect-names = "ddr";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -777,6 +787,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c2_default>;
pinctrl-1 = <&blsp1_i2c2_sleep>;
+ interconnects = <&pnoc 86 &bimc 512>;
+ interconnect-names = "ddr";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -792,6 +804,8 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_spi5_default>;
pinctrl-1 = <&blsp2_spi5_sleep>;
+ interconnects = <&pnoc 78 &bimc 512>;
+ interconnect-names = "ddr";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -811,6 +825,8 @@
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
+ interconnects = <&pnoc 81 &bimc 512>;
+ interconnect-names = "ddr";
bus-width = <4>;
};
@@ -1082,6 +1098,9 @@
assigned-clock-rates = <19200000>, <60000000>;
power-domains = <&gcc USB30_GDSC>;
+
+ interconnects = <&pnoc 87 &bimc 512>;
+ interconnect-names = "ddr";
status = "disabled";
dwc3@7600000 {
@@ -1110,6 +1129,9 @@
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
+ interconnects = <&pnoc 61 &bimc 512>;
+ interconnect-names = "ddr";
+
power-domains = <&gcc USB30_GDSC>;
status = "disabled";
@@ -1182,6 +1204,8 @@
"bus_master",
"bus_slave";
+ interconnects = <&a0noc 45 &bimc 512>;
+ interconnect-names = "ddr";
};
pcie1: qcom,pcie@608000 {
@@ -1237,6 +1261,9 @@
"cfg",
"bus_master",
"bus_slave";
+
+ interconnects = <&a0noc 100 &bimc 512>;
+ interconnect-names = "ddr";
};
pcie2: qcom,pcie@610000 {
@@ -1291,6 +1318,9 @@
"cfg",
"bus_master",
"bus_slave";
+
+ interconnects = <&a0noc 108 &bimc 512>;
+ interconnect-names = "ddr";
};
};
@@ -1367,6 +1397,10 @@
<0 0>;
lanes-per-direction = <1>;
+
+ interconnects = <&a2noc 95 &bimc 512>, <&bimc 1 &cnoc 650>;
+ interconnect-names = "ddr", "cfg";
+
status = "disabled";
ufs_variant {
@@ -1502,6 +1536,9 @@
iommus = <&mdp_smmu 0>;
+ interconnects = <&mmnoc 22 &bimc 512>, <&mmnoc 23 &bimc 512>, <&mmnoc 25 &bimc 512>;
+ interconnect-names = "port0", "port1", "rotator";
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1676,6 +1713,190 @@
clock-names = "iface", "bus";
status = "okay";
};
+
+ venus_smmu: arm,smmu-venus@d40000 {
+ compatible = "arm,smmu-v2";
+ reg = <0xd40000 0x20000>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
+ clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
+ <&mmcc SMMU_VIDEO_AXI_CLK>;
+ clock-names = "smmu_core_ahb_clk",
+ "smmu_core_axi_clk";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
+ venus: video-codec@c00000 {
+ compatible = "qcom,msm8996-venus";
+ reg = <0x00c00000 0xff000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mmcc VENUS_GDSC>;
+ clocks = <&mmcc VIDEO_CORE_CLK>,
+ <&mmcc VIDEO_AHB_CLK>,
+ <&mmcc VIDEO_AXI_CLK>,
+ <&mmcc VIDEO_MAXI_CLK>;
+ clock-names = "core", "iface", "bus", "mbus";
+ iommus = <&venus_smmu 0x00>,
+ <&venus_smmu 0x01>,
+ <&venus_smmu 0x0a>,
+ <&venus_smmu 0x07>,
+ <&venus_smmu 0x0e>,
+ <&venus_smmu 0x0f>,
+ <&venus_smmu 0x08>,
+ <&venus_smmu 0x09>,
+ <&venus_smmu 0x0b>,
+ <&venus_smmu 0x0c>,
+ <&venus_smmu 0x0d>,
+ <&venus_smmu 0x10>,
+ <&venus_smmu 0x11>,
+ <&venus_smmu 0x21>,
+ <&venus_smmu 0x28>,
+ <&venus_smmu 0x29>,
+ <&venus_smmu 0x2b>,
+ <&venus_smmu 0x2c>,
+ <&venus_smmu 0x2d>,
+ <&venus_smmu 0x31>;
+ memory-region = <&venus_region>;
+
+ interconnects = <&mmnoc 63 &bimc 512>;
+ interconnect-names = "ddr";
+
+ status = "disabled";
+
+ video-decoder {
+ compatible = "venus-decoder";
+ clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE0_GDSC>;
+ };
+
+ video-encoder {
+ compatible = "venus-encoder";
+ clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE1_GDSC>;
+ };
+ };
+
+ bimc: bimc@400000 {
+ compatible = "qcom,msm8996-bimc";
+ #interconnect-cells = <1>;
+ reg = <0x400000 0x62000>;
+ type = <2>;
+ base-offset = <0x8000>;
+ qos-offset = <0x4000>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>, <&rpmcc RPM_SMD_BIMC_A_CLK>;
+// &mmagic_bimc_noc_cfg_ahb_clk.clkr.hw,
+ status = "okay";
+ };
+
+ cnoc: cnoc@500000 {
+ compatible = "qcom,msm8996-cnoc";
+ #interconnect-cells = <1>;
+ reg = <0x500000 0x80>;
+ type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_CNOC_CLK>, <&rpmcc RPM_SMD_CNOC_A_CLK>;
+ status = "okay";
+ };
+
+ snoc: snoc@520000 {
+ compatible = "qcom,msm8996-snoc";
+ #interconnect-cells = <1>;
+ reg = <0x520000 0xa100>;
+ type = <1>;
+ base-offset = <0x4000>;
+ qos-offset = <0x1000>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>, <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ status = "okay";
+ };
+
+ a0noc: a0noc@540000 {
+ compatible = "qcom,msm8996-a0noc";
+ #interconnect-cells = <1>;
+ reg = <0x540000 0x5100>;
+ type = <1>;
+ qcom,base-offset = <0x3000>;
+ qos-offset = <0x1000>;
+ clock-names = "bus_clk", "bus_a_clk";
+/*
+ &gcc_aggre0_snoc_axi_clk.clkr.hw,
+ &gcc_aggre0_cnoc_ahb_clk.clkr.hw,
+ &gcc_smmu_aggre0_axi_clk.clkr.hw,
+ &gcc_smmu_aggre0_ahb_clk.clkr.hw,
+*/
+ clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, <&gcc GCC_AGGRE0_SNOC_AXI_CLK>;
+ power-domains = <&gcc AGGRE0_NOC_GDSC>;
+ status = "okay";
+ };
+
+ a1noc: a1noc@560000 {
+ compatible = "qcom,msm8996-a1noc";
+ #interconnect-cells = <1>;
+ reg = <0x560000 0x3100>;
+ type = <1>;
+ base-offset = <0x2000>;
+ qos-offset = <0x1000>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
+ status = "okay";
+ };
+
+ a2noc: a2noc@580000 {
+ compatible = "qcom,msm8996-a2noc";
+ #interconnect-cells = <1>;
+ reg = <0x580000 0x8100>;
+ base-offset = <0x3000>;
+ qos-offset = <0x1000>;
+ type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
+ status = "okay";
+ };
+
+ mmnoc: mmnoc@5a0000 {
+ compatible = "qcom,msm8996-mmnoc";
+ #interconnect-cells = <1>;
+ reg = <0x5a0000 0xb080>;
+ type = <1>;
+ base-offset = <0x4000>;
+ qos-offset = <0x1000>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, <&rpmcc RPM_SMD_MMAXI_A_CLK>;
+/*
+ &mmss_mmagic_ahb_clk.clkr.hw,
+ &mmss_mmagic_cfg_ahb_clk.clkr.hw,
+ &mmagic_video_axi_clk.clkr.hw,
+ &mmagic_video_noc_cfg_ahb_clk.clkr.hw,
+ &mmagic_mdss_axi_clk.clkr.hw,
+ &mmagic_mdss_noc_cfg_ahb_clk.clkr.hw,
+ &mmagic_camss_axi_clk.clkr.hw,
+ &mmagic_camss_noc_cfg_ahb_clk.clkr.hw,
+*/
+ power-domains = <&mmcc MMAGIC_BIMC_GDSC>;
+ status = "okay";
+ };
+
+ pnoc: pnoc@5c0000 {
+ compatible = "qcom,msm8996-pnoc";
+ #interconnect-cells = <1>;
+ reg = <0x5c0000 0x2480>;
+ type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, <&rpmcc RPM_SMD_PCNOC_A_CLK>;
+ status = "okay";
+ };
};
adsp-pil {
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-22 08:03:09 +0000