diff options
Diffstat (limited to 'Documentation')
5 files changed, 129 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 4491d1c104aa..87b4949e9bc8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -16,6 +16,7 @@ Required properties : "qcom,rpmcc-msm8974", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" + "qcom,rpmcc-qcs404", "qcom,rpmcc" - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt new file mode 100644 index 000000000000..301987e716fd --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,snps-28nm-usb-hs-phy.txt @@ -0,0 +1,87 @@ +Qualcomm Synopsys 28nm Femto phy controller +=========================================== + +Synopsys 28nm femto phy controller supports LS/FS/HS usb connectivity on +Qualcomm chipsets. + +Required properties: + +- compatible: + Value type: <string> + Definition: Should contain "qcom,qcs404-usb-hsphy". + +- reg: + Value type: <prop-encoded-array> + Definition: USB PHY base address and length of the register map. + +- #phy-cells: + Value type: <u32> + Definition: Should be 0. See phy/phy-bindings.txt for details. + +- clocks: + Value type: <prop-encoded-array> + Definition: See clock-bindings.txt section "consumers". List of + three clock specifiers for reference, phy core and + sleep clocks. + +- clock-names: + Value type: <string> + Definition: Names of the clocks in 1-1 correspondence with the "clocks" + property. Must contain "ref", "phy" and "sleep". + +- resets: + Value type: <prop-encoded-array> + Definition: See reset.txt section "consumers". PHY reset specifiers + for phy core and POR resets. + +- reset-names: + Value type: <string> + Definition: Names of the resets in 1-1 correspondence with the "resets" + property. Must contain "phy" and "por". + +- vdd-supply: + Value type: <phandle> + Definition: phandle to the regulator VDD supply node. + +- vdda1p8-supply: + Value type: <phandle> + Definition: phandle to the regulator 1.8V supply node. + +- vdda3p3-supply: + Value type: <phandle> + Definition: phandle to the regulator 3.3V supply node. + +- qcom,vdd-voltage-level: + Value type: <prop-array> + Definition: This is a list of three integer values <no min max> where + each value corresponding to voltage corner in uV. + +Optional child nodes: + +- The link to the USB connector should be modeled using the OF graph bindings + specified in bindings/graph.txt. + +Example: + + phy@7a000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x7a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + qcom,vdd-voltage-level = <0 1144000 1200000>; + + port { + ep_usb_phy: endpoint { + remote-endpoint = <&ep_usb_con>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index ab4000eab07d..759aa1732e48 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -92,7 +92,7 @@ to specify in a pin configuration subnode: gpio1-gpio26 for pm8998 gpio1-gpio22 for pma8084 gpio1-gpio10 for pmi8994 - gpio1-gpio11 for pms405 + gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) - function: Usage: required diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt index 89e1cb9212f6..ec95705ba692 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt @@ -23,6 +23,7 @@ resources. "qcom,rpm-msm8916" "qcom,rpm-msm8974" "qcom,rpm-msm8998" + "qcom,rpm-qcs404" - qcom,smd-channels: Usage: required diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt new file mode 100644 index 000000000000..ecf21dadf187 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt @@ -0,0 +1,39 @@ +Qualcomm Technologies, Inc. MSM PHY Transceivers + +Required properties: + +- compatible: Should be "qcom,usb-ssphy" +- reg: Address and length of the register set for the device +- clocks: a list of handles to the PHY clocks. Use as per + Documentation/devicetree/bindings/clock/clock-bindings.txt +- clock-names: Names of the clocks in 1-1 correspondence with the "clocks" + property. "ref_clk", "cfg_ahb_clk" and "pipe_clk" are mandatory. + +- <supply-name>-supply: phandle to the regulator device tree node + Required "supply-name" examples are: + "vdd" : vdd supply for SSPHY digital circuit operation + "vdda18" : 1.8v high-voltage analog supply for SSPHY + +- qcom,vdd-voltage-level: This property must be a list of three integer +values (no, min, max) where each value represents either a voltage in +microvolts or a value corresponding to voltage corner + +Optional properties: + +- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to +the USB PHY and the controller must rely on external VBUS notification in +order to manually relay the notification to the SSPHY. + +Example: + +ssphy@f9200000 { + compatible = "qcom,usb-ssphy"; + reg = <0xf9200000 0xfc000>; + vdd-supply = <&pm8841_s2_corner>; + vdda18-supply = <&pm8941_l6>; + qcom,vdd-voltage-level = <1 5 7>; + clocks = <&clock_gcc USB_PHY_REF_CLK>, + <&clock_gcc USB_PHY_CFG_AHB_CLK>, + <&clock_gcc USB_PHY_PIPE_CLK>; + clock-names = "ref_clk", "cfg_ahb_clk", "pipe_clk"; +}; |