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author | Linaro CI <ci_notify@linaro.org> | 2020-09-19 21:59:09 +0000 |
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committer | Linaro CI <ci_notify@linaro.org> | 2020-09-19 21:59:09 +0000 |
commit | dba97c7eeabad4fd8cef356f689a28d6a2bc53fc (patch) | |
tree | 9f2450dd4ded35d0feb609a516a46f806ad5415a /drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | |
parent | cfbb440280f1dc7be488069b1e8aa67720c73a81 (diff) | |
parent | 6c73ce02692d9e32e34885368180a744079fa9f9 (diff) |
Merge remote-tracking branch 'sm8250/tracking-qcomlt-sm8250' into integration-linux-qcomltintegration-linux-qcomlt-20200920-093824-v5.9-rc5-435-gdba97c7eeaba
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c')
-rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c new file mode 100644 index 000000000000..bf63bfbcdec2 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + */ + +#include <linux/iopoll.h> + +#include "dpu_hw_mdss.h" +#include "dpu_hwio.h" +#include "dpu_hw_catalog.h" +#include "dpu_hw_merge3d.h" +#include "dpu_kms.h" +#include "dpu_trace.h" + +#define MERGE_3D_MUX 0x000 +#define MERGE_3D_MODE 0x004 + +static const struct dpu_merge_3d_cfg *_merge_3d_offset(enum dpu_merge_3d pp, + const struct dpu_mdss_cfg *m, + void __iomem *addr, + struct dpu_hw_blk_reg_map *b) +{ + int i; + + for (i = 0; i < m->merge_3d_count; i++) { + if (pp == m->merge_3d[i].id) { + b->base_off = addr; + b->blk_off = m->merge_3d[i].base; + b->length = m->merge_3d[i].len; + b->hwversion = m->hwversion; + b->log_mask = DPU_DBG_MASK_PINGPONG; + return &m->merge_3d[i]; + } + } + + return ERR_PTR(-EINVAL); +} + +static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d, + enum dpu_3d_blend_mode mode_3d) +{ + struct dpu_hw_blk_reg_map *c; + u32 data; + + + c = &merge_3d->hw; + data = BIT(0) | ((mode_3d - 1) << 1); + pr_info("MERGE 3D MODE %d %d %x\n", merge_3d->base.id, mode_3d, data); + DPU_REG_WRITE(c, MERGE_3D_MODE, data); +} + +static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c, + unsigned long features) +{ + c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode; +}; + +static struct dpu_hw_blk_ops dpu_hw_ops; + +struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(enum dpu_merge_3d idx, + void __iomem *addr, + const struct dpu_mdss_cfg *m) +{ + struct dpu_hw_merge_3d *c; + const struct dpu_merge_3d_cfg *cfg; + + c = kzalloc(sizeof(*c), GFP_KERNEL); + if (!c) + return ERR_PTR(-ENOMEM); + + cfg = _merge_3d_offset(idx, m, addr, &c->hw); + if (IS_ERR_OR_NULL(cfg)) { + kfree(c); + return ERR_PTR(-EINVAL); + } + + c->idx = idx; + c->caps = cfg; + _setup_merge_3d_ops(c, c->caps->features); + + dpu_hw_blk_init(&c->base, DPU_HW_BLK_MERGE_3D, idx, &dpu_hw_ops); + + return c; +} + +void dpu_hw_merge_3d_destroy(struct dpu_hw_merge_3d *pp) +{ + if (pp) + dpu_hw_blk_destroy(&pp->base); + kfree(pp); +} |