diff options
author | Linaro CI <ci_notify@linaro.org> | 2022-07-19 13:38:22 +0000 |
---|---|---|
committer | Linaro CI <ci_notify@linaro.org> | 2022-07-19 13:38:22 +0000 |
commit | 8c1018313ca06c4887c95b40f02d4965314fe80b (patch) | |
tree | cd55a8e55ee9656520015ece9eae6574d03e2288 | |
parent | 63b1eff6102091e1230a89cef00fd4be602476b8 (diff) | |
parent | 577d39fac258a8b852226486ac231a8f2760ad39 (diff) |
Merge remote-tracking branch 'msm8939/tracking-qcomlt-msm8939' into integration-linux-qcomltintegration-linux-qcomlt-20220719-150755-v5.19-rc7-287-g8c1018313ca06c
57 files changed, 5899 insertions, 303 deletions
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 5c06d1bfc046..e85a1d85b877 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -34,6 +34,7 @@ description: | mdm9615 msm8226 msm8916 + msm8939 msm8974 msm8992 msm8994 @@ -139,6 +140,12 @@ properties: - items: - enum: + - sony,kanuti-tulip + - square,apq8039-t2 + - const: qcom,msm8939 + + - items: + - enum: - qcom,msm8960-cdp - const: qcom,msm8960 diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 880bfe930830..d7cc702f5a5d 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -35,22 +35,67 @@ properties: - description: Display escape clock - description: Display AHB clock - description: Display AXI clock + - description: Core MultiMedia SubSystem clock + - description: MDP Core clock + - description: MNOC clock + minItems: 6 + maxItems: 9 clock-names: - items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus + oneOf: + - items: + - const: byte + - const: byte_intf + - const: pixel + - const: core + - const: iface + - const: bus + - items: + - const: mdp_core + - const: byte + - const: byte_intf + - const: mnoc + - const: iface + - const: bus + - const: core_mmss + - const: pixel + - const: core + - items: + - const: mdp_core + - const: byte + - const: iface + - const: bus + - const: core_mmss + - const: pixel + - const: core + - items: + - const: mdp_core + - const: iface + - const: bus + - const: byte + - const: pixel + - const: core + - const: core_mmss + - items: + - const: mdp_core + - const: iface + - const: bus + - const: byte + - const: pixel + - const: core + - items: + # DSI v2 + - const: iface + - const: bus + - const: core_mmss + - const: src + - const: byte + - const: pixel + - const: core phys: maxItems: 1 - phy-names: - const: dsi - "#address-cells": true "#size-cells": true @@ -125,6 +170,18 @@ properties: - port@0 - port@1 + vdd-supply: + description: + Phandle to vdd regulator device node + + vddio-supply: + description: + Phandle to vdd-io regulator device node + + vdda-supply: + description: + Phandle to vdda regulator device node + required: - compatible - reg @@ -133,11 +190,9 @@ required: - clocks - clock-names - phys - - phy-names - assigned-clocks - assigned-clock-parents - power-domains - - operating-points-v2 - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml index 3d8540a06fe2..f76ffb031409 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -19,12 +19,33 @@ properties: - qcom,dsi-phy-28nm-lp - qcom,dsi-phy-28nm-8960 + clocks: + minItems: 2 + + clock-names: + items: + - const: iface + description: AHB clock + - const: ref + description: Block reference clock + minItems: 2 + + '#clock-cells': + const: 1 + + "#phy-cells": + const: 0 + reg: items: - description: dsi pll register set - description: dsi phy register set - description: dsi phy regulator register set + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: Indicates if the LDO mode PHY regulator is wanted. + reg-names: items: - const: dsi_pll @@ -36,6 +57,10 @@ properties: required: - compatible + - clocks + - clock-names + - "#clock-cells" + - "#phy-cells" - reg - reg-names - vddio-supply diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 3397bc31d087..a750dc2a2579 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -58,7 +58,7 @@ properties: - const: ocmem iommus: - maxItems: 1 + maxItems: 2 sram: $ref: /schemas/types.yaml#/definitions/phandle-array diff --git a/Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.yaml b/Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.yaml index 6a9c96f0352a..1bc412a4ac5e 100644 --- a/Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.yaml +++ b/Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.yaml @@ -27,10 +27,14 @@ properties: interrupt-names: minItems: 1 - items: - - const: usb_id - - const: usb_vbus - + anyOf: + - items: + - const: usb_id + - const: usb_vbus + - items: + - const: usb_id + - items: + - const: usb_vbus required: - compatible - reg diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 3b5ba7ecc19d..f504652fc0ea 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -15,26 +15,30 @@ maintainers: properties: compatible: - enum: - - qcom,ipq6018-apcs-apps-global - - qcom,ipq8074-apcs-apps-global - - qcom,msm8916-apcs-kpss-global - - qcom,msm8939-apcs-kpss-global - - qcom,msm8953-apcs-kpss-global - - qcom,msm8976-apcs-kpss-global - - qcom,msm8994-apcs-kpss-global - - qcom,msm8996-apcs-hmss-global - - qcom,msm8998-apcs-hmss-global - - qcom,qcm2290-apcs-hmss-global - - qcom,qcs404-apcs-apps-global - - qcom,sc7180-apss-shared - - qcom,sc8180x-apss-shared - - qcom,sdm660-apcs-hmss-global - - qcom,sdm845-apss-shared - - qcom,sm6125-apcs-hmss-global - - qcom,sm6115-apcs-hmss-global - - qcom,sm8150-apss-shared - + oneOf: + - items: + - enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + - qcom,msm8976-apcs-kpss-global + - qcom,msm8996-apcs-hmss-global + - qcom,msm8998-apcs-hmss-global + - qcom,qcm2290-apcs-hmss-global + - qcom,sc7180-apss-shared + - qcom,sc8180x-apss-shared + - qcom,sdm660-apcs-hmss-global + - qcom,sdm845-apss-shared + - qcom,sm6125-apcs-hmss-global + - qcom,sm6115-apcs-hmss-global + - qcom,sm8150-apss-shared + - items: + - enum: + - qcom,msm8916-apcs-kpss-global + - qcom,msm8939-apcs-kpss-global + - qcom,msm8953-apcs-kpss-global + - qcom,msm8994-apcs-kpss-global + - qcom,qcs404-apcs-apps-global + - const: syscon reg: maxItems: 1 @@ -121,7 +125,7 @@ examples: #define GCC_APSS_AHB_CLK_SRC 1 #define GCC_GPLL0_AO_OUT_MAIN 123 apcs: mailbox@b011000 { - compatible = "qcom,qcs404-apcs-apps-global"; + compatible = "qcom,qcs404-apcs-apps-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index ba51fb1252b9..6b5b9b422ad5 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -90,6 +90,9 @@ Optional properties: case, the "idle" state needs to pull down the data and strobe pin and the "active" state needs to pull up the strobe pin. - pinctrl-n: alternate pin modes +- pin-switch-delay-us: the optional delay time in (us) to allow for the + application of a pinctrl-n state switch. + i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f4c245d44db3..19c96c11bde4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb @@ -18,6 +19,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts new file mode 100644 index 000000000000..18cdc3b65183 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd. + * + */ + +/dts-v1/; + +#include "msm8939.dtsi" +#include "pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/sound/apq8016-lpass.h> + +/ { + model = "Square, Inc. T2 Devkit"; + compatible = "square,apq8039-t2", "qcom,msm8939"; + qcom,board-id = <0x53 0x54>; + + aliases { + serial0 = &blsp1_uart1; + serial1 = &blsp1_uart2; + }; + + bl: backlight { + compatible = "gpio-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + gpios = <&msmgpio 98 GPIO_ACTIVE_HIGH>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + lcd_iovcc_vreg: lcd-iovcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_iovcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_iovcc>; + gpios = <&msmgpio 9 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + }; + + lcd_avdd_vreg: lcd-avdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_avdd"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_avdd>; + gpios = <&msmgpio 86 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + }; + + lcd_avee_vreg: lcd-avee-regulator { + compatible = "regulator-fixed"; + regulator-name = "lcd_avee"; + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_avee>; + gpios = <&msmgpio 87 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + }; + + pp_spe_3v3_vreg: pp-spe-3v3-regulator { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&msmgpio_spe_reg>; + regulator-name = "pp_spe_3v3"; + gpios = <&msmgpio 108 GPIO_ACTIVE_HIGH>; + startup-delay-us = <0>; + enable-active-high; + }; + + pp_crq_3v3_vreg: pp-crq-3v3-regulator { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&msmgpio_crq_reg>; + regulator-name = "pp_crq_3v3"; + gpios = <&msmgpio 12 GPIO_ACTIVE_HIGH>; + startup-delay-us = <0>; + enable-active-high; + }; +}; + +&blsp_dma { + status = "okay"; +}; + +&blsp_i2c1 { + status = "okay"; +}; + +&blsp_i2c2 { + status = "okay"; +}; + +&blsp_i2c3 { + status = "okay"; + tps6598x: tps6598x@38 { + compatible = "ti,tps6598x"; + reg = <0x38>; + + interrupt-parent = <&msmgpio>; + interrupts = <107 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + + pinctrl-names = "default"; + pinctrl-0 = <&typec_pins>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + port { + typec_ep: endpoint { + remote-endpoint = <&otg_ep>; + }; + }; + }; + }; +}; + +&blsp_i2c5 { + status = "okay"; +}; + +&blsp1_uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart1_default>; + pinctrl-1 = <&blsp1_uart1_sleep>; + status = "okay"; +}; + +&blsp1_uart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + status = "okay"; +}; + +&lpass { + status = "okay"; +}; + +&mdss_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <&truly_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel@0 { + compatible = "truly,r63350-fhd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + iovcc-supply = <&lcd_iovcc_vreg>; + avdd-supply = <&lcd_avdd_vreg>; + avee-supply = <&lcd_avee_vreg>; + reset-gpios = <&msmgpio 25 GPIO_ACTIVE_LOW>; + backlight = <&bl>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + truly_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0_phy { + vddio-supply = <&pm8916_l6>; + status = "okay"; +}; + +/* + * Line names are taken from the schematic of T2, Ver X03. + * July 14, 2018. Page 4 in particular. + */ + +&msmgpio { + gpio-line-names = + "APQ_UART1_TX", /* GPIO_0 */ + "APQ_UART1_RX", + "APQ_I2C1_SDA", + "APQ_I2C1_SCL", + "APQ_UART2_TX_1V8", + "APQ_UART2_RX_1V8", + "APQ_I2C2_SDA", + "APQ_I2C2_SCL", + "NC", + "APQ_LCD_IOVCC_EN", + "APQ_I2C3_SDA", /* GPIO_10 */ + "APQ_I2C3_SCL", + "TOUCH_RST_1V8_L", + "NC", + "APQ_I2C4_SDA", + "APQ_I2C4_SCL", + "APQ_ID5", + "USB_DISCONNECT", + "APQ_I2C5_SDA", + "APQ_I2C5_SCL", + "APQ_USBC_SPI_MOSI", /* GPIO_20 */ + "APQ_USBC_SPI_MISO", + "APQ_USBC_SPI_SS_L", + "APQ_USBC_SPI_CLK", + "APQ_LCD_TE0", + "APQ_LCD_RST_L", + "NC", + "NC", + "ACCELEROMETER_INT1", + "APQ_CAM_I2C0_SDA", + "APQ_CAM_I2C0_SCL", /* GPIO_30 */ + "ACCELEROMETER_INT2", + "NC", + "NC", + "NC", + "APQ_K21_RST_1V8_L", + "NC", + "APQ_EDL_1V8", + "TP145", + "BT_SSBI", + "NC", /* GPIO_40 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "BT_CTRL", + "BT_DAT", + "PWR_GPIO_IN", + "PWR_GPIO_OUT", /* GPIO_50 */ + "CARD_DET_MLB_L", + "HALL_SENSOR", + "TP63", + "TP64", + "TP65", + "NC", + "NC", + "NC", + "NC", + "NC", /* GPIO_60 */ + "NC", + "APQ_K21_GPIO0_1V8", + "CDC_PDM_CLK", + "CDC_PDM_SYNC", + "CDC_PDM_TX", + "CDC_PDM_RX0", + "CDC_PDM_RX1", + "CDC_PDM_RX2", + "APQ_K21_GPIO1_1V8", + "NC", /* GPIO_70 */ + "APQ_HUB_SEL_1V8", + "APQ_K21_GPIO2_1V8", + "APQ_K21_GPIO3_1V8", + "APQ_ID0", + "APQ_ID1", + "APQ_ID2", + "APQ_ID3", + "APQ_ID4", + "APQ_HUB_SUSP_IND", + "BOOT_CONFIG_0", /* GPIO_80 */ + "BOOT_CONFIG_1", + "BOOT_CONFIG_2", + "BOOT_CONFIG_3", + "NC", + "NC", + "APQ_LCD_AVDD_EN", + "APQ_LCD_AVEE_EN", + "TP70", + "NC", + "APQ_DEBUG0", /* GPIO_90 */ + "APQ_DEBUG1", + "APQ_DEBUG2", + "APQ_DEBUG3", + "TP165", + "NC", + "APQ_LNA_PWR_EN", + "NC", + "APQ_LCD_BL_EN", + "NC", + "APQ_LCD_ID0", /* GPIO_100 */ + "APQ_LCD_ID1", + "USBC_GPIO5_1V8", + "NC", + "NC", + "NC", + "APQ_HUB_RST_1V8_L", + "USBC_I2C_IRQ_1V8_L", + "SPE_PWR_EN", + "NC", + "APQ_USB_ID", /* GPIO_110 */ + "APQ_EXT_BUCK_VSEL", + "APQ_USB_ID_OUT", + "NC", + "PRNT_RST_L", + "APQ_CRQ_I2C_RDY_1V8", + "TYPEC_RST_1V8_H", + "CHG_BACKPWR_EN", + "CHG_PROCHOT_L", + "NC", + "USBC_GPIO7_1V8", /* GPIO_120 */ + "NC"; + + blsp1_uart1_default: blsp1-uart1-default { + pins = "gpio0", "gpio1"; + function = "blsp_uart1"; + + drive-strength = <16>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep { + pins = "gpio0", "gpio1"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + pinctrl_lcd_iovcc: lcd-iovcc { + pins = "gpio9"; + function = "gpio"; + }; + + pinctrl_lcd_avdd: lcd-avdd { + pins = "gpio86"; + function = "gpio"; + }; + + pinctrl_lcd_avee: lcd-avee { + pins = "gpio87"; + function = "gpio"; + }; + + pinctrl_backlight: backlight { + pins = "gpio98"; + function = "gpio"; + }; + + pinctrl_panel: panel { + pins = "gpio25"; + function = "gpio"; + }; + + msmgpio_spe_reg: msmgpio-spe-reg { + pins = "gpio108"; + function = "gpio"; + output-high; + }; + + sq_spe_enable: sq-spe-enable { + pins = "gpio35"; + function = "gpio"; + output-low; + }; + + msmgpio_crq_reg: msmgpio-crq-reg { + function = "gpio"; + pins = "gpio12"; + output-high; + }; + + typec_pins: typec-pins { + function = "gpio"; + pins = "gpio107"; + bias-pull-up; + input-enable; + }; + + pinctrl_otg_default: otg-default { + function = "gpio"; + pins = "gpio17"; + output-high; + }; + + pinctrl_otg_host: otg-host { + function = "gpio"; + pins = "gpio17"; + output-low; + }; + + pinctrl_otg_device: otg-device { + function = "gpio"; + pins = "gpio17"; + output-low; + }; + + ext_buck_vsel: ext-buck-vsel { + label = "ext-buck-vsel"; + function = "gpio"; + pins = "gpio111"; + drive-strength = <2>; + }; +}; + +&pm8916_gpios { + gpio-line-names = + "PM_GPIO1", /* WIFI_GPIO1_PRE */ + "PM_GPIO2", /* WIFI_GPIO2_PRE */ + "PM_GPIO3", + "PM_GPIO4"; +}; + +&remoteproc_pronto { + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + status = "okay"; + + iris { + compatible = "qcom,wcn3680"; + }; +}; + +&rpm_requests { + smd_rpm_regulators: pm8916-regulators { + compatible = "qcom,rpm-pm8916-regulators"; + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + pm8916_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8916_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + /* l1 is fixed to 1225000, but not connected in schematic */ + pm8916_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8916_l4: l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8916_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l8: l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l10: l10 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l11: l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8916_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8916_l18: l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8916_l8>; + vqmmc-supply = <&pm8916_l5>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + status = "okay"; +}; + +&sound { + status = "okay"; + pinctrl-0 = <&cdc_pdm_lines_act>; + pinctrl-1 = <&cdc_pdm_lines_sus>; + pinctrl-names = "default", "sleep"; + model = "apq8039-square-sndcard"; + audio-routing = "AMIC2", "MIC BIAS Internal2"; + + internal-codec-playback-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + }; + }; + + internal-codec-capture-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + }; + }; +}; + +&usb { + status = "okay"; + usb-role-switch; + + pinctrl-names = "default", "host", "device"; + pinctrl-0 = <&pinctrl_otg_default>; + pinctrl-1 = <&pinctrl_otg_host>; + pinctrl-2 = <&pinctrl_otg_device>; + pin-switch-delay-us = <100000>; + + ulpi { + usb_hs_phy: phy { + qcom,enable-vbus-pullup; + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; + }; + }; + port { + otg_ep: endpoint { + remote-endpoint = <&typec_ep>; + }; + }; +}; + +&wcd_codec { + status = "okay"; + qcom,hphl-jack-type-normally-open; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 05472510e29d..392517398e82 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1030,7 +1030,6 @@ "pixel", "core"; phys = <&dsi_phy0>; - phy-names = "dsi-phy"; #address-cells = <1>; #size-cells = <0>; @@ -1422,7 +1421,7 @@ lpass: audio-controller@7708000 { status = "disabled"; - compatible = "qcom,lpass-cpu-apq8016"; + compatible = "qcom,apq8016-lpass-cpu"; /* * Note: Unlike the name would suggest, the SEC_I2S_CLK diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts new file mode 100644 index 000000000000..03b84c3a0aad --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Bryan O'Donoghue. + * + */ + +/dts-v1/; + +#include "msm8939.dtsi" +#include "pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + model = "Sony Xperia M4 Aqua"; + compatible = "sony,kanuti-tulip", "qcom,msm8939"; + qcom,board-id = <8 0>; + + aliases { + serial0 = &blsp1_uart2; + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + negative5_vreg: negative5-vreg { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&msmgpio_negative5_vreg>; + regulator-name = "negative5_vreg"; + gpios = <&msmgpio 17 GPIO_ACTIVE_LOW>; + startup-delay-us = <0>; + enable-active-low; + }; + + positive5_vreg: positive5-vreg { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&msmgpio_positive5_vreg>; + regulator-name = "positive5_vreg"; + gpios = <&msmgpio 114 GPIO_ACTIVE_LOW>; + startup-delay-us = <0>; + enable-active-low; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; +}; + +&blsp_dma { + status = "okay"; +}; + +&mdss_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l16>; + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel@0 { + compatible = "sony,tulip-truly-nt35521"; + reg = <0>; + positive5-supply = <&positive5_vreg>; + negative5-supply = <&negative5_vreg>; + reset-gpios = <&msmgpio 25 GPIO_ACTIVE_LOW>; + enable-gpios = <&msmgpio 10 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + + }; +}; + +&mdss_dsi0_phy { + vddio-supply = <&pm8916_l16>; + status = "okay"; +}; + +&msmgpio { + + ak8963_default: ak8963-default { + pins = "gpio69"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + ak8963_sleep: ak8963-sleep { + pins = "gpio69"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + /* Ambient light and proximity sensor apds9930 and apds9900 */ + apds99xx_default: apds99xx-default { + pins = "gpio113"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + apds99xx_sleep: apds99xx-sleep { + pins = "gpio113"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + cam_sensor_flash_default: default { + pins = "gpio98", "gpio97"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + cci1_default: cci1-default { + pins = "gpio31", "gpio32"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + cdc_ext_spk_pa_active: cdc-ext-spk-pa-on { + pins = "gpio0"; + function = "gpio"; + drive-strength = <8>; + output-low; + bias-pull-none; + }; + + cdc_ext_spk_pa_sus: cdc-ext-spk-pa-off { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cdc_slim_lines_act: lines-on { + pins = "gpio63"; + function = "cdc_pdm0"; + drive-strength = <8>; + output-high; + bias-pull-none; + }; + + cdc_slim_lines_sus: lines-off { + pins = "gpio63"; + function = "cdc_pdm0"; + drive-strength = <2>; + bias-disable; + }; + + cross_conn_det_act: lines-on { + pins = "gpio120"; + function = "gpio"; + drive-strength = <8>; + output-low; + bias-pull-down; + }; + + cross_conn_det_sus: lines-off { + pins = "gpio120"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + ext_buck_vsel: vsel0 { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + }; + + ext_cdc_tlmm_lines_act: tlmm-lines-on { + pins = "gpio116", "gpio112", "gpio117", "gpio118", "gpio119"; + function = "gpio"; + drive-strength = <8>; + }; + + ext_cdc_tlmm_lines_sus: tlmm-lines-off { + pins = "gpio116", "gpio112", "gpio117", "gpio118", "gpio119"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_key_suspend: gpio-key-suspend { + pins = "gpio107", "gpio108", "gpio109"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + msmgpio_negative5_vreg: msmgpio-negative5-vreg { + pins = "gpio17"; + function = "gpio"; + output-low; + bias-pull-none; + }; + + msmgpio_positive5_vreg: msmgpio-positive5-vreg { + pins = "gpio114"; + function = "gpio"; + output-low; + bias-pull-none; + }; + + /* Gyroscope and accelerometer sensor combo */ + mpu6050_default: mpu6050-default { + pins = "gpio115"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + mpu6050_sleep: mpu6050-sleep { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc_disable_active: nfc-disable-active { + pins = "gpio20"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + nfc_disable_suspend: nfc-disable-suspend { + pins = "gpio20"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + nfc_int_active: nfc-int-active { + pins = "gpio21"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + nfc_int_suspend: nfc-int-suspend { + pins = "gpio21"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + nt35521_te_default: nt35521-te-default { + pins = "gpio24"; + function = "gpio"; + drive-strength = <6>; + bias-pull-down; + }; + + nt35521_backlight: nt35521-backlight { + pins = "gpio10"; + function = "gpio"; + drive-strength = <6>; + bias-pull-down; + }; + + smb_int: smb-int { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + /* add pingrp for touchscreen */ + ts_int_active: ts-int-active { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + ts_int_suspend: ts-int-suspend { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_reset_active: ts-reset-active { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + ts_reset_suspend: ts-reset-suspend { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_release: ts-release { + pins = "gpio13", "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + usb_id_default: usb_id_default { + pins = "gpio110"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; + +&remoteproc_pronto { + status = "okay"; +}; + +&rpm_requests { + smd_rpm_regulators: pm8916-regulators { + compatible = "qcom,rpm-pm8916-regulators"; + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + pm8916_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8916_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + pm8916_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8916_l4: l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8916_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8916_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8916_l8: l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + pm8916_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l10: l10 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l11: l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8916_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8916_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8916_l18: l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + }; +}; + +&sdhc_1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + status = "okay"; +}; + +&sdhc_2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usb { + status = "okay"; + extcon = <&usb_id>, <&usb_id>; + + ulpi { + usb_hs_phy: phy { + qcom,enable-vbus-pullup; + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; + }; + }; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi new file mode 100644 index 000000000000..201df9b5837a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -0,0 +1,2441 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2022, Linaro Limited + */ + +#include <dt-bindings/clock/qcom,gcc-msm8939.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interconnect/qcom,msm8939.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/reset/qcom,gcc-msm8939.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + qcom,msm-id = <239 0>, <239 0x30000>, <241 0x30000>, <263 0x30000>; + + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@100 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x100>; + next-level-cache = <&L2_1>; + power-domains = <&vreg_dummy>; + power-domain-names = "cpr"; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_SPC>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + L2_1: l2-cache@1 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + cpu1: cpu@101 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x101>; + next-level-cache = <&L2_1>; + power-domains = <&vreg_dummy>; + power-domain-names = "cpr"; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + }; + + cpu2: cpu@102 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x102>; + next-level-cache = <&L2_1>; + power-domains = <&vreg_dummy>; + power-domain-names = "cpr"; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + }; + + cpu3: cpu@103 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x103>; + next-level-cache = <&L2_1>; + power-domains = <&vreg_dummy>; + power-domain-names = "cpr"; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + clocks = <&apcs1_mbox>; + #cooling-cells = <2>; + }; + + cpu4: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x0>; + qcom,acc = <&acc4>; + qcom,saw = <&saw4>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + power-domains = <&vreg_dummy>; + power-domain-names = "cpr"; + L2_0: l2-cache@0 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + cpu5: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x1>; + next-level-cache = <&L2_0>; + power-domains = <&vreg_dummy>; + power-domain-names = "cpr"; + qcom,acc = <&acc5>; + qcom,saw = <&saw5>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + }; + + cpu6: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x2>; + next-level-cache = <&L2_0>; + power-domains = <&vreg_dummy>; + power-domain-names = "cpr"; + qcom,acc = <&acc6>; + qcom,saw = <&saw6>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + }; + + cpu7: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "spin-table"; + reg = <0x3>; + next-level-cache = <&L2_0>; + power-domains = <&vreg_dummy>; + power-domain-names = "cpr"; + qcom,acc = <&acc7>; + qcom,saw = <&saw7>; + clocks = <&apcs0_mbox>; + #cooling-cells = <2>; + }; + + idle-states { + CPU_SPC: spc { + compatible ="qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <130>; + exit-latency-us = <150>; + min-residency-us = <2000>; + local-timer-stop; + }; + }; + }; + + /* + * MSM8939 has a big.LITTLE hetrogeneous computing architecture, + * consisting of two clusters of four ARM Cortex-A53s each. The + * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs + * at 1.5-1.7GHz. + * + * The enable method used here is spin-table which pre-supposes use + * of a 2nd stage boot shim such as lk2nd to have installed a + * spin-table, the downstream non-psci/non-spin-table method that + * default msm8916/msm8936/msm8939 will not be supported upstream. + */ + cpu-map { + /* LITTLE (efficiency) cluster */ + cluster0 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + + /* big (performance) cluster */ + /* Boot CPU is cluster 1 core 0 */ + cluster1 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8916"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + + qcom,dload-mode = <&tcsr 0x6100>; + }; + }; + + hexagon-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs1_mbox 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + hexagon_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8)| IRQ_TYPE_LEVEL_HIGH)>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz-apps@86000000 { + reg = <0x0 0x86000000 0x0 0x300000>; + no-map; + }; + + smem_mem: smem@86300000 { + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + }; + + hypervisor@86400000 { + reg = <0x0 0x86400000 0x0 0x100000>; + no-map; + }; + + tz@86500000 { + reg = <0x0 0x86500000 0x0 0x180000>; + no-map; + }; + + reserved@86680000 { + reg = <0x0 0x86680000 0x0 0x1000>; + no-map; + }; + + rmtfs@86681000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x86681000 0x0 0x15f000>; + no-map; + qcom,client-id = <1>; + }; + + rfsa@867e0000 { + reg = <0x0 0x867e0000 0x0 0x20000>; + no-map; + }; + + mpss_mem: mpss@86800000 { + reg = <0x0 0x86800000 0x0 0x5500000>; + no-map; + }; + + wcnss_mem: wcnss@8bd00000 { + reg = <0x0 0x8bd00000 0x0 0x600000>; + no-map; + }; + + venus_mem: venus@8c300000 { + reg = <0x0 0x8c300000 0x0 0x800000>; + no-map; + }; + + mba_mem: mba@8cb00000 { + no-map; + reg = <0x0 0x8cb00000 0x0 0x100000>; + }; + }; + + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs1_mbox 8 13>; + qcom,ipc-3 = <&apcs1_mbox 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + rng@22000 { + compatible = "qcom,prng"; + reg = <0x00022000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + qfprom: qfprom@5c000 { + compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; + reg = <0x0005c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@a0 { + reg = <0xa0 0x5c>; + }; + cpr_efuse_init_voltage1: ivoltage1@dc { + reg = <0xdc 0x4>; + bits = <4 6>; + }; + cpr_efuse_init_voltage2: ivoltage2@da { + reg = <0xda 0x4>; + bits = <2 6>; + }; + cpr_efuse_init_voltage3: ivoltage3@d8 { + reg = <0xd8 0x4>; + bits = <0 6>; + }; + cpr_efuse_quot1: quot1@dc { + reg = <0xdd 0x8>; + bits = <2 12>; + }; + cpr_efuse_quot2: quot2@da { + reg = <0xdb 0x8>; + bits = <0x0 12>; + }; + cpr_efuse_quot3: quot3@d8 { + reg = <0xd8 0x8>; + bits = <6 12>; + }; + cpr_efuse_ring1: ring1@de { + reg = <0xde 0x4>; + bits = <6 3>; + }; + cpr_efuse_ring2: ring2@de { + reg = <0xde 0x4>; + bits = <6 3>; + }; + cpr_efuse_ring3: ring3@de { + reg = <0xde 0x4>; + bits = <6 3>; + }; + cpr_efuse_revision: revision@4 { + reg = <0x5 0x1>; + bits = <5 1>; + }; + cpr_efuse_revision_high: revision-high@4 { + reg = <0x7 0x1>; + bits = <0 1>; + }; + cpr_efuse_pvs_version: pvs@4 { + reg = <0x3 0x1>; + bits = <5 1>; + }; + cpr_efuse_pvs_version_high: pvs-high@4 { + reg = <0x6 0x1>; + bits = <2 2>; + }; + cpr_efuse_speedbin: speedbin@c { + reg = <0xc 0x1>; + bits = <2 3>; + }; + + }; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x00060000 0x8000>; + }; + + bimc: interconnect@400000 { + compatible = "qcom,msm8939-bimc"; + reg = <0x00400000 0x62000>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, + <&rpmcc RPM_SMD_BIMC_A_CLK>; + #interconnect-cells = <1>; + status = "okay"; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <10>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow"; + #thermal-sensor-cells = <1>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x004ab000 0x4>; + }; + + pcnoc: interconnect@500000 { + compatible = "qcom,msm8939-pcnoc"; + reg = <0x00500000 0x11000>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_PCNOC_A_CLK>; + #interconnect-cells = <1>; + status = "okay"; + }; + + snoc: interconnect@580000 { + compatible = "qcom,msm8939-snoc"; + reg = <0x00580000 0x14080>; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, + <&rpmcc RPM_SMD_SNOC_A_CLK>; + #interconnect-cells = <1>; + status = "okay"; + + snoc_mm: interconnect@580000 { + compatible = "qcom,msm8939-snoc-mm"; + clock-names = "bus", "bus_a"; + clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>, + <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>; + #interconnect-cells = <1>; + status = "okay"; + }; + + }; + + msmgpio: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 122>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1_uart1_default: blsp1-uart1-default { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + + drive-strength = <16>; + bias-disable; + }; + + blsp1_uart1_sleep: blsp1-uart1-sleep { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + blsp1_uart2_default: blsp1-uart2-default { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + + drive-strength = <16>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep { + pins = "gpio4", "gpio5"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + camera_front_default: camera-front-default { + pwdn { + pins = "gpio33"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + rst { + pins = "gpio28"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + mclk1 { + pins = "gpio27"; + function = "cam_mclk1"; + + drive-strength = <16>; + bias-disable; + }; + }; + + camera_rear_default: camera-rear-default { + pwdn { + pins = "gpio34"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + rst { + pins = "gpio35"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + mclk0 { + pins = "gpio26"; + function = "cam_mclk0"; + + drive-strength = <16>; + bias-disable; + }; + }; + + cci0_default: cci0-default { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + + drive-strength = <16>; + bias-disable; + }; + + cdc-pdm-lines { + cdc_pdm_lines_act: pdm-lines-on { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + + drive-strength = <8>; + bias-disable; + }; + cdc_pdm_lines_sus: pdm-lines-off { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + function = "cdc_pdm0"; + + drive-strength = <2>; + bias-pull-down; + }; + }; + + cdc-dmic-lines { + cdc_dmic_lines_act: dmic-lines-on { + clk { + pins = "gpio0"; + function = "dmic0_clk"; + + drive-strength = <8>; + }; + data { + pins = "gpio1"; + function = "dmic0_data"; + + drive-strength = <8>; + }; + }; + cdc_dmic_lines_sus: dmic-lines-off { + clk { + pins = "gpio0"; + function = "dmic0_clk"; + + drive-strength = <2>; + bias-disable; + }; + data { + pins = "gpio1"; + function = "dmic0_data"; + + drive-strength = <2>; + bias-disable; + }; + }; + }; + + ext-mclk-tlmm-lines { + ext_mclk_tlmm_lines_act: mclk-lines-on { + pins = "gpio116"; + function = "pri_mi2s"; + + drive-strength = <8>; + bias-disable; + }; + ext_mclk_tlmm_lines_sus: mclk-lines-off { + pins = "gpio116"; + function = "pri_mi2s"; + + drive-strength = <2>; + bias-disable; + }; + }; + + ext-pri-tlmm-lines { + ext_pri_tlmm_lines_act: ext-pa-on { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + + drive-strength = <8>; + bias-disable; + }; + ext_pri_tlmm_lines_sus: ext-pa-off { + pins = "gpio113", "gpio114", "gpio115", "gpio116"; + function = "pri_mi2s"; + + drive-strength = <2>; + bias-disable; + }; + }; + + ext-pri-ws-line { + ext_pri_ws_act: ext-pa-on { + pins = "gpio110"; + function = "pri_mi2s_ws"; + + drive-strength = <8>; + bias-disable; + }; + ext_pri_ws_sus: ext-pa-off { + pins = "gpio110"; + function = "pri_mi2s_ws"; + + drive-strength = <2>; + bias-disable; + }; + }; + + /* secondary Mi2S */ + ext-sec-tlmm-lines { + ext_sec_tlmm_lines_act: tlmm-lines-on { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + + drive-strength = <8>; + bias-disable; + }; + ext_sec_tlmm_lines_sus: tlmm-lines-off { + pins = "gpio112", "gpio117", "gpio118", "gpio119"; + function = "sec_mi2s"; + + drive-strength = <2>; + bias-disable; + }; + }; + + i2c1_default: i2c1-default { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + + drive-strength = <2>; + bias-disable; + }; + + i2c1_sleep: i2c1-sleep { + pins = "gpio2", "gpio3"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + i2c2_default: i2c2-default { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + + drive-strength = <2>; + bias-disable; + }; + + i2c2_sleep: i2c2-sleep { + pins = "gpio6", "gpio7"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + i2c3_default: i2c3-default { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + + drive-strength = <2>; + bias-disable; + }; + + i2c3_sleep: i2c3-sleep { + pins = "gpio10", "gpio11"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + i2c4_default: i2c4-default { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + + drive-strength = <2>; + bias-disable; + }; + + i2c4_sleep: i2c4-sleep { + pins = "gpio14", "gpio15"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + i2c5_default: i2c5-default { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + + drive-strength = <2>; + bias-disable; + }; + + i2c5_sleep: i2c5-sleep { + pins = "gpio18", "gpio19"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + i2c6_default: i2c6-default { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + + drive-strength = <2>; + bias-disable; + }; + + i2c6_sleep: i2c6-sleep { + pins = "gpio22", "gpio23"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + pmx-sdc1-clk { + sdc1_clk_on: clk-on { + pins = "sdc1_clk"; + + bias-disable; + drive-strength = <16>; + }; + sdc1_clk_off: clk-off { + pins = "sdc1_clk"; + + bias-disable; + drive-strength = <2>; + }; + }; + + pmx-sdc1-cmd { + sdc1_cmd_on: cmd-on { + pins = "sdc1_cmd"; + + bias-pull-up; + drive-strength = <10>; + }; + sdc1_cmd_off: cmd-off { + pins = "sdc1_cmd"; + + bias-pull-up; + drive-strength = <2>; + }; + }; + + pmx-sdc1-data { + sdc1_data_on: data-on { + pins = "sdc1_data"; + + bias-pull-up; + drive-strength = <10>; + }; + sdc1_data_off: data-off { + pins = "sdc1_data"; + + bias-pull-up; + drive-strength = <2>; + }; + }; + + pmx-sdc2-clk { + sdc2_clk_on: clk-on { + pins = "sdc2_clk"; + + bias-disable; + drive-strength = <16>; + }; + sdc2_clk_off: clk-off { + pins = "sdc2_clk"; + + bias-disable; + drive-strength = <2>; + }; + }; + + pmx-sdc2-cmd { + sdc2_cmd_on: cmd-on { + pins = "sdc2_cmd"; + + bias-pull-up; + drive-strength = <10>; + }; + sdc2_cmd_off: cmd-off { + pins = "sdc2_cmd"; + + bias-pull-up; + drive-strength = <2>; + }; + }; + + pmx-sdc2-data { + sdc2_data_on: data-on { + pins = "sdc2_data"; + + bias-pull-up; + drive-strength = <10>; + }; + sdc2_data_off: data-off { + pins = "sdc2_data"; + + bias-pull-up; + drive-strength = <2>; + }; + }; + + pmx-sdc2-cd-pin { + sdc2_cd_on: cd-on { + pins = "gpio38"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + sdc2_cd_off: cd-off { + pins = "gpio38"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + }; + + spi1_default: spi1-default { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + + drive-strength = <12>; + bias-disable; + + cs { + pins = "gpio2"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi1_sleep: spi1-sleep { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + spi2_default: spi2-default { + pins = "gpio4", "gpio5", "gpio7"; + function = "blsp_spi2"; + + drive-strength = <12>; + bias-disable; + + cs { + pins = "gpio6"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi2_sleep: spi2-sleep { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + spi3_default: spi3-default { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + + drive-strength = <12>; + bias-disable; + + cs { + pins = "gpio10"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi3_sleep: spi3-sleep { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + spi4_default: spi4-default { + pins = "gpio12", "gpio13", "gpio15"; + function = "blsp_spi4"; + + drive-strength = <12>; + bias-disable; + + cs { + pins = "gpio14"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi4_sleep: spi4-sleep { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + spi5_default: spi5-default { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + + drive-strength = <12>; + bias-disable; + + cs { + pins = "gpio18"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi5_sleep: spi5-sleep { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + spi6_default: spi6-default { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + + drive-strength = <12>; + bias-disable; + + cs { + pins = "gpio22"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi6_sleep: spi6-sleep { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + wcnss_pin_a: wcnss-active { + pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; + function = "wcss_wlan"; + + drive-strength = <6>; + bias-pull-up; + }; + + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8939"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board>, <&sleep_clk>; + clock-names = "xo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + tcsr_mutex_regs: hwlock@1905000 { + compatible = "qcom,tcsr-msm8916", "syscon"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8916", "syscon"; + reg = <0x01937000 0x30000>; + }; + + mdss: mdss@1a00000 { + compatible = "qcom,mdss"; + reg = <0x01a00000 0x1000>, + <0x01ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, + <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + mdss_mdp: mdp@1a01000 { + compatible = "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDP_TBU_CLK>, + <&gcc GCC_MDP_RT_TBU_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "tbu", + "tbu_rt"; + + iommus = <&apps_iommu 4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@1a98000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x01a98000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi-phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: dsi-phy@1a98300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x01a98300 0xd4>, + <0x01a98500 0x280>, + <0x01a98780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + qcom,dsi-phy-regulator-ldo-mode; + status = "disabled"; + }; + + mdss_dsi1: dsi@1aa0000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x01aa0000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc BYTE1_CLK_SRC>, + <&gcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + phys = <&mdss_dsi1_phy>; + phy-names = "dsi-phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: dsi-phy@1aa0300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x01aa0300 0xd4>, + <0x01aa0500 0x280>, + <0x01aa0780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + qcom,dsi-phy-regulator-ldo-mode; + status = "disabled"; + }; + }; + + gpu@1c00000 { + compatible = "qcom,adreno-405.0", "qcom,adreno"; + reg = <0x01c00000 0x10000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + clock-names = "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d", + "rbbmtimer"; + clocks = <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>, + <&gcc GCC_OXILI_TIMER_CLK>; + power-domains = <&gcc OXILI_GDSC>; + operating-points-v2 = <&opp_table>; + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + + opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + }; + + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + }; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; + }; + + venus: video-codec@1d00000 { + compatible = "qcom,msm8939-venus"; + reg = <0x01d00000 0xff000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&gcc VENUS_GDSC>; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>; + clock-names = "core", "iface", "bus"; + + interconnects = <&bimc MASTER_AMPSS_M0 &pcnoc SLAVE_VENUS_CFG>, + <&snoc_mm MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>; + interconnect-names = "cpu-cfg", "video-mem"; + + iommus = <&apps_iommu 5>; + memory-region = <&venus_mem>; + + resets = <&gcc GCC_VENUS0_BCR>; + status = "okay"; + + video-decoder { + compatible = "venus-decoder"; + clocks = <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>; + clock-names = "vcodec0_core"; + power-domains = <&gcc VENUS_CORE0_GDSC>; + }; + + video-encoder { + compatible = "venus-encoder"; + clocks = <&gcc GCC_VENUS0_CORE1_VCODEC0_CLK>; + clock-names = "vcodec1_core"; + power-domains = <&gcc VENUS_CORE1_GDSC>; + }; + }; + + apps_iommu: iommu@1ef0000 { + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + reg = <0x01ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + ranges = <0 0x1e20000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + qcom,iommu-secure-id = <17>; + + /* mdp_0: */ + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* venus_ns: */ + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>, + <&gcc GCC_GFX_TBU_CLK>; + clock-names = "iface", "bus", "tlb"; + ranges = <0 0x1f08000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + qcom,iommu-secure-id = <18>; + + /* gfx3d_user: */ + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* gfx3d_priv: */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x400000>, + <0x02c00000 0x400000>, + <0x03800000 0x200000>, + <0x0200a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + remoteproc_mss: remoteproc@4080000 { + compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; + reg = <0x04080000 0x100>, + <0x04020000 0x040>; + + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + power-domains = <&rpmpd MSM8939_VDDMDCX_AO>, + <&rpmpd MSM8939_VDDMX>; + power-domain-names = "cx", "mx"; + pll-supply = <&pm8916_l7>; + + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&scm 0>; + reset-names = "mss_restart"; + + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + + smd-edge { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + qcom,smd-edge = <0>; + mboxes = <&apcs1_mbox 12>; + qcom,remote-pid = <1>; + + label = "hexagon"; + }; + }; + + sound: sound@7702000 { + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, + <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + status = "disabled"; + }; + + lpass: audio-controller@7708000 { + compatible = "qcom,apq8016-lpass-cpu"; + reg = <0x07708000 0x10000>; + reg-names = "lpass-lpaif"; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpass-irq-lpaif"; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; + clock-names = "ahbix-clk", + "mi2s-bit-clk0", + "mi2s-bit-clk1", + "mi2s-bit-clk2", + "mi2s-bit-clk3", + "pcnoc-mport-clk", + "pcnoc-sway-clk"; + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpass_codec: audio-codec@771c000 { + compatible = "qcom,msm8916-wcd-digital-codec"; + reg = <0x0771c000 0x400>; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "ahbix-clk", "mclk"; + #sound-dai-cells = <1>; + }; + + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp_i2c1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_default>; + pinctrl-1 = <&i2c3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_default>; + pinctrl-1 = <&i2c4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c5: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_default>; + pinctrl-1 = <&i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_default>; + pinctrl-1 = <&i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi2: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x500>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x500>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi4: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x500>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_default>; + pinctrl-1 = <&spi5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi6: spi@78ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078ba000 0x500>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi6_default>; + pinctrl-1 = <&spi6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdhc_1: sdhci@7824000 { + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x11c>, + <0x07824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: sdhci@7864000 { + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, + <0x07864000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + reset-names = "core"; + #reset-cells = <1>; + bus-width = <4>; + status = "disabled"; + }; + + usb: usb@78d9000 { + compatible = "qcom,ci-hdrc"; + reg = <0x078d9000 0x200>, + <0x078d9200 0x200>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + #reset-cells = <1>; + phy_type = "ulpi"; + dr_mode = "otg"; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + + ulpi { + usb_hs_phy: phy { + compatible = "qcom,usb-hs-phy-msm8916", + "qcom,usb-hs-phy"; + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names = "phy", "por"; + #phy-cells = <0>; + qcom,init-seq = /bits/ 8 <0x0 0x44 + 0x1 0x6b 0x2 0x24 0x3 0x13>; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + apcs1_mbox: mailbox@b011000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b011000 0x1000>; + clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&xo_board>; + clock-names = "pll", "aux", "ref"; + #clock-cells = <0>; + assigned-clocks = <&apcs2>; + assigned-clock-rates = <297600000>; + #mbox-cells = <1>; + }; + + a53pll_c1: clock@b016000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b016000 0x40>; + #clock-cells = <0>; + }; + + acc0: clock-controller@b088000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b088000 0x1000>; + }; + + saw0: power-manager@b089000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b089000 0x1000>; + }; + + acc1: clock-controller@b098000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b098000 0x1000>; + }; + + saw1: power-manager@b099000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b099000 0x1000>; + }; + + acc2: clock-controller@b0a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0a8000 0x1000>; + }; + + saw2: power-manager@b0a9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0a9000 0x1000>; + }; + + acc3: clock-controller@b0b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b0b8000 0x1000>; + }; + + saw3: power-manager@b0b9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b0b9000 0x1000>; + }; + + apcs0_mbox: mailbox@b111000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b111000 0x1000>; + clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&xo_board>; + clock-names = "pll", "aux", "ref"; + #clock-cells = <0>; + #mbox-cells = <1>; + }; + + a53pll_c0: clock@b116000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + }; + + acc4: clock-controller@b188000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b188000 0x1000>; + }; + + saw4: power-manager@b189000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b189000 0x1000>; + }; + + acc5: clock-controller@b198000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b198000 0x1000>; + }; + + saw5: power-manager@b199000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b199000 0x1000>; + }; + + acc6: clock-controller@b1a8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b1a8000 0x1000>; + }; + + saw6: power-manager@b1a9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b1a9000 0x1000>; + }; + + acc7: clock-controller@b1b8000 { + compatible = "qcom,kpss-acc-v2"; + reg = <0x0b1b8000 0x1000>; + }; + + saw7: power-manager@b1b9000 { + compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; + reg = <0x0b1b9000 0x1000>; + }; + + a53pll_cci: clock@b1d0000 { + compatible = "qcom,msm8939-a53pll"; + reg = <0x0b1d0000 0x40>; + #clock-cells = <0>; + }; + + apcs2: mailbox@b1d1000 { + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; + reg = <0x0b1d1000 0x1000>; + clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&xo_board>; + clock-names = "pll", "aux", "ref"; + #clock-cells = <0>; + #mbox-cells = <1>; + }; + + timer@b020000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b020000 0x1000>; + clock-frequency = <19200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b021000 { + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b021000 0x1000>, + <0x0b022000 0x1000>; + }; + + frame@b023000 { + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b023000 0x1000>; + status = "disabled"; + }; + + frame@b024000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b024000 0x1000>; + status = "disabled"; + }; + + frame@b025000 { + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b025000 0x1000>; + status = "disabled"; + }; + + frame@b026000 { + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b026000 0x1000>; + status = "disabled"; + }; + + frame@b027000 { + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b027000 0x1000>; + status = "disabled"; + }; + + frame@b028000 { + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b028000 0x1000>; + status = "disabled"; + }; + }; + + remoteproc_pronto: remoteproc@a204000 { + compatible = "qcom,pronto-v2-pil"; + reg = <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + memory-region = <&wcnss_mem>; + + power-domains = <&rpmpd MSM8939_VDDCX>, + <&rpmpd MSM8939_VDDMX_AO>; + power-domain-names = "cx", "mx"; + vddpx-supply = <&pm8916_l7>; + + qcom,state = <&wcnss_smp2p_out 0>; + qcom,state-names = "stop"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + status = "disabled"; + + iris { + compatible = "qcom,wcn3660"; + + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; + }; + + smd-edge { + interrupts = <GIC_SPI 142 1>; + + qcom,ipc = <&apcs1_mbox 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&remoteproc_pronto>; + + bt { + compatible = "qcom,wcnss-bt"; + }; + + wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, + <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs1_mbox 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm_requests { + compatible = "qcom,rpm-msm8936"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-manager { + compatible = "qcom,msm8939-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu0_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu1_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu2_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu3_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu3_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4567-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + cpu4567_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu4567_crit: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu4567_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens 3>; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens 0>; + }; + + modem2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens 2>; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens 1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + vreg_dummy: regulator-dummy { + #power-domain-cells = <0>; + }; + + wcnss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs1_mbox 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index e76f7967bfc3..5b0798dd0a5f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -941,7 +941,6 @@ "core"; phys = <&dsi0_phy>; - phy-names = "dsi"; status = "disabled"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/pm6350.dtsi b/arch/arm64/boot/dts/qcom/pm6350.dtsi index c5d85064562b..ecf9b9919182 100644 --- a/arch/arm64/boot/dts/qcom/pm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6350.dtsi @@ -36,9 +36,10 @@ }; pm6350_gpios: gpios@c000 { - compatible = "qcom,pm6350-gpio"; + compatible = "qcom,pm6350-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm6350_gpios 0 0 9>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index c482663aad56..d0eefbb51663 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -171,7 +171,7 @@ }; pm660_gpios: gpios@c000 { - compatible = "qcom,pm660-gpio"; + compatible = "qcom,pm660-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; gpio-ranges = <&pm660_gpios 0 0 13>; diff --git a/arch/arm64/boot/dts/qcom/pm8009.dtsi b/arch/arm64/boot/dts/qcom/pm8009.dtsi index b126d7e7e4fb..0c2c424be0ea 100644 --- a/arch/arm64/boot/dts/qcom/pm8009.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8009.dtsi @@ -19,9 +19,10 @@ }; pm8009_gpios: gpio@c000 { - compatible = "qcom,pm8005-gpio"; + compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8009_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 0df76f7b1cc1..fd8434215924 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -127,9 +127,10 @@ }; pm8150_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio"; + compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8150_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 5cd4268e74b8..c365b75898bc 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -119,9 +119,10 @@ }; pm8150b_gpios: gpio@c000 { - compatible = "qcom,pm8150b-gpio"; + compatible = "qcom,pm8150b-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8150b_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index a236e3d439b0..25e94697e048 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -100,9 +100,10 @@ }; pm8150l_gpios: gpio@c000 { - compatible = "qcom,pm8150l-gpio"; + compatible = "qcom,pm8150l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8150l_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index b10f33afa5e3..2dfeb99300d7 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -45,9 +45,10 @@ }; pm8350_gpios: gpio@8800 { - compatible = "qcom,pm8350-gpio"; + compatible = "qcom,pm8350-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pm8350_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index f1d1d4c8edf8..f1c7bd9d079c 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -45,9 +45,10 @@ }; pm8350b_gpios: gpio@8800 { - compatible = "qcom,pm8350b-gpio"; + compatible = "qcom,pm8350b-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pm8350b_gpios 0 0 8>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index d58902432812..0b6e8ad7fa50 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -108,14 +108,13 @@ }; pm8916_gpios: gpios@c000 { - compatible = "qcom,pm8916-gpio"; + compatible = "qcom,pm8916-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8916_gpios 0 0 4>; #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index 7072e5a2e73f..68e9122363ae 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -116,7 +116,7 @@ }; pmm8155au_1_gpios: gpio@c000 { - compatible = "qcom,pmm8155au-gpio"; + compatible = "qcom,pmm8155au-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi index 72075964fbb9..c307fc662511 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -89,7 +89,7 @@ }; pmm8155au_2_gpios: gpio@c000 { - compatible = "qcom,pmm8155au-gpio"; + compatible = "qcom,pmm8155au-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index 604324188603..ec24c4478005 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -45,9 +45,10 @@ }; pmr735b_gpios: gpio@8800 { - compatible = "qcom,pmr735b-gpio"; + compatible = "qcom,pmr735b-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pmr735b_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 98d173a377d5..634b0681d04c 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -38,22 +38,13 @@ #size-cells = <0>; pms405_gpios: gpio@c000 { - compatible = "qcom,pms405-gpio"; + compatible = "qcom,pms405-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pms405_gpios 0 0 12>; #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pon@800 { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 5dcaac23a138..b0e8b07d54c1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3017,7 +3017,6 @@ power-domains = <&rpmhpd SC7180_CX>; phys = <&dsi_phy>; - phy-names = "dsi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e66fc67de206..0b22b9857828 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3552,7 +3552,6 @@ power-domains = <&rpmhpd SC7280_CX>; phys = <&mdss_dsi_phy>; - phy-names = "dsi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index b72e8e6c52f3..a90be5e7245e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1561,7 +1561,6 @@ "core"; phys = <&dsi0_phy>; - phy-names = "dsi"; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index 1d748c5305f4..5f85708eba23 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -190,7 +190,6 @@ "core"; phys = <&dsi1_phy>; - phy-names = "dsi"; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index dd387207cdee..70807bf3438e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4447,7 +4447,6 @@ power-domains = <&rpmhpd SDM845_CX>; phys = <&dsi0_phy>; - phy-names = "dsi"; status = "disabled"; @@ -4519,7 +4518,6 @@ power-domains = <&rpmhpd SDM845_CX>; phys = <&dsi1_phy>; - phy-names = "dsi"; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index acd37851c763..18b3e9f0a56d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3667,7 +3667,6 @@ power-domains = <&rpmhpd SM8250_MMCX>; phys = <&dsi0_phy>; - phy-names = "dsi"; status = "disabled"; @@ -3740,7 +3739,6 @@ power-domains = <&rpmhpd SM8250_MMCX>; phys = <&dsi1_phy>; - phy-names = "dsi"; status = "disabled"; diff --git a/arch/arm64/configs/db410c_defconfig b/arch/arm64/configs/db410c_defconfig new file mode 100644 index 000000000000..36cffb497e4a --- /dev/null +++ b/arch/arm64/configs/db410c_defconfig @@ -0,0 +1,497 @@ +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_FHANDLE is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_QCOM=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=64 +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=2 +CONFIG_CRASH_DUMP=y +CONFIG_ARM64_SW_TTBR0_PAN=y +CONFIG_COMPAT=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_HIBERNATION=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM_DEBUG=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MEMORY_FAILURE=y +CONFIG_CMA=y +CONFIG_CMA_AREAS=7 +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IPVTI=y +CONFIG_INET_ESP=y +CONFIG_INET_UDP_DIAG=y +CONFIG_INET_DIAG_DESTROY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_VTI=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_CT=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_BPF=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_OWNER=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_L2TP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_NETEM=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_CLS_BPF=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_DNS_RESOLVER=y +CONFIG_QRTR=y +CONFIG_QRTR_SMD=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_QCOMSMD=m +CONFIG_CFG80211=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_RFKILL=y +CONFIG_NET_9P=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_SPI_NOR=y +CONFIG_ZRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_QCOM_COINCELL=y +CONFIG_SRAM=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_VERITY=y +CONFIG_DM_VERITY_FEC=y +CONFIG_NETDEVICES=y +CONFIG_TUN=y +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_MPPE=y +CONFIG_PPTP=y +CONFIG_PPPOL2TP=y +CONFIG_USB_USBNET=y +CONFIG_WCN36XX=m +CONFIG_WCN36XX_DEBUGFS=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=y +CONFIG_TABLET_USB_AIPTEK=y +CONFIG_TABLET_USB_HANWANG=y +CONFIG_TABLET_USB_KBTAB=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y +CONFIG_INPUT_UINPUT=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM is not set +# CONFIG_DEVMEM is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_QUP=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPMI=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_MSM8916=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_BQ27XXX=y +CONFIG_THERMAL=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_DRM=y +CONFIG_DRM_MSM=y +CONFIG_DRM_PANEL_TRULY_R65530=y +CONFIG_FB=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_QCOM=y +CONFIG_SND_SOC_APQ8016_SBC=y +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y +CONFIG_HIDRAW=y +CONFIG_UHID=y +CONFIG_HID_A4TECH=y +CONFIG_HID_ACRUX=y +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_PRODIKEYS=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=y +CONFIG_HID_ELECOM=y +CONFIG_HID_EZKEY=y +CONFIG_HID_HOLTEK=y +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_LOGITECH_DJ=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=y +CONFIG_HID_PANTHERLORD=y +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_PICOLCD=y +CONFIG_HID_PRIMAX=y +CONFIG_HID_ROCCAT=y +CONFIG_HID_SAITEK=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SPEEDLINK=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_WACOM=y +CONFIG_HID_WIIMOTE=y +CONFIG_HID_ZEROPLUS=y +CONFIG_HID_ZYDACRON=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_PRINTER=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_HUB_USB251XB=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_SNP_UDC_PLAT=y +CONFIG_USB_BDC_UDC=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_FUNCTIONFS=m +CONFIG_TYPEC=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PM8XXX=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR_V2=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_STAGING=y +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_A53PLL=y +CONFIG_QCOM_CLK_APCS_MSM8916=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_MSM_GCC_8916=y +CONFIG_MSM_GCC_8939=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_MAILBOX=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_QCOM_IOMMU=y +CONFIG_REMOTEPROC=y +CONFIG_QCOM_WCNSS_PIL=m +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_RPMSG_QCOM_SMD=y +CONFIG_QCOM_CPR=y +CONFIG_QCOM_RPMPD=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMP2P=y +CONFIG_QCOM_SMSM=y +CONFIG_QCOM_SOCINFO=y +CONFIG_QCOM_WCNSS_CTRL=m +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_IIO=y +CONFIG_QCOM_SPMI_VADC=y +CONFIG_PWM=y +CONFIG_QCOM_MPM=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_QCOM_QFPROM=y +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_MSM8939=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_EFIVAR_FS=y +CONFIG_SQUASHFS=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_SECURITY_SELINUX=y +CONFIG_INIT_STACK_NONE=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_INDIRECT_PIO=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_SCHEDSTATS=y +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_RCU_TRACE is not set +CONFIG_ENABLE_DEFAULT_TRACERS=y +CONFIG_MEMTEST=y diff --git a/arch/arm64/configs/square_defconfig b/arch/arm64/configs/square_defconfig new file mode 100644 index 000000000000..a0d63bd88e89 --- /dev/null +++ b/arch/arm64/configs/square_defconfig @@ -0,0 +1,500 @@ +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_FHANDLE is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_QCOM=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=64 +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=2 +CONFIG_CRASH_DUMP=y +CONFIG_ARM64_SW_TTBR0_PAN=y +CONFIG_COMPAT=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_HIBERNATION=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM_DEBUG=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MEMORY_FAILURE=y +CONFIG_CMA=y +CONFIG_CMA_AREAS=7 +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IPVTI=y +CONFIG_INET_ESP=y +CONFIG_INET_UDP_DIAG=y +CONFIG_INET_DIAG_DESTROY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_VTI=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_CT=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_BPF=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_OWNER=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_L2TP=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_NETEM=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_CLS_BPF=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_DNS_RESOLVER=y +CONFIG_QRTR=y +CONFIG_QRTR_SMD=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_QCOMSMD=m +CONFIG_CFG80211=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_RFKILL=y +CONFIG_NET_9P=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEBUG_DRIVER=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_SPI_NOR=y +CONFIG_ZRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_QCOM_COINCELL=y +CONFIG_SRAM=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_VERITY=y +CONFIG_DM_VERITY_FEC=y +CONFIG_NETDEVICES=y +CONFIG_TUN=y +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_MPPE=y +CONFIG_PPTP=y +CONFIG_PPPOL2TP=y +CONFIG_USB_USBNET=y +CONFIG_WCN36XX=m +CONFIG_WCN36XX_DEBUGFS=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=y +CONFIG_TABLET_USB_AIPTEK=y +CONFIG_TABLET_USB_HANWANG=y +CONFIG_TABLET_USB_KBTAB=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y +CONFIG_INPUT_UINPUT=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_QUP=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPMI=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_MSM8916=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_BQ27XXX=y +CONFIG_THERMAL=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_QCOM_TSENS=y +CONFIG_WATCHDOG=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_DRM=y +CONFIG_DRM_MSM=y +CONFIG_DRM_PANEL_TRULY_R65530=y +CONFIG_FB=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_QCOM=y +CONFIG_SND_SOC_APQ8016_SBC=y +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=y +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y +CONFIG_HIDRAW=y +CONFIG_UHID=y +CONFIG_HID_A4TECH=y +CONFIG_HID_ACRUX=y +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_PRODIKEYS=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=y +CONFIG_HID_ELECOM=y +CONFIG_HID_EZKEY=y +CONFIG_HID_HOLTEK=y +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_LOGITECH_DJ=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=y +CONFIG_HID_PANTHERLORD=y +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_PICOLCD=y +CONFIG_HID_PRIMAX=y +CONFIG_HID_ROCCAT=y +CONFIG_HID_SAITEK=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SPEEDLINK=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +CONFIG_HID_WACOM=y +CONFIG_HID_WIIMOTE=y +CONFIG_HID_ZEROPLUS=y +CONFIG_HID_ZYDACRON=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_PRINTER=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_HUB_USB251XB=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_SNP_UDC_PLAT=y +CONFIG_USB_BDC_UDC=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_TYPEC=y +CONFIG_TYPEC_TPS6598X=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_SYSCON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PM8XXX=y +CONFIG_DMADEVICES=y +CONFIG_MV_XOR_V2=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +CONFIG_STAGING=y +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_A53PLL=y +CONFIG_QCOM_CLK_APCS_MSM8916=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_MSM_GCC_8916=y +CONFIG_MSM_GCC_8939=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_MAILBOX=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_QCOM_IOMMU=y +CONFIG_REMOTEPROC=y +CONFIG_QCOM_WCNSS_PIL=m +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_QCOM_SMD=y +CONFIG_QCOM_CPR=y +CONFIG_QCOM_RPMPD=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMP2P=y +CONFIG_QCOM_SMSM=y +CONFIG_QCOM_SOCINFO=y +CONFIG_QCOM_SPM=y +CONFIG_QCOM_WCNSS_CTRL=m +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_IIO=y +CONFIG_QCOM_SPMI_VADC=y +CONFIG_PWM=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_QCOM_QFPROM=y +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_MSM8939=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_EFIVAR_FS=y +CONFIG_SQUASHFS=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_SECURITY_SELINUX=y +CONFIG_INIT_STACK_NONE=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_INDIRECT_PIO=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_SCHEDSTATS=y +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_RCU_TRACE is not set +CONFIG_ENABLE_DEFAULT_TRACERS=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_MEMTEST=y diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c index 39ebb443ae3d..754d5573b1df 100644 --- a/drivers/clk/qcom/gcc-msm8939.c +++ b/drivers/clk/qcom/gcc-msm8939.c @@ -1002,7 +1002,8 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { }; static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = { - F(19200000, P_XO, 1, 0, 0), + F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0, 1, 3, 64), { } }; @@ -1142,6 +1143,9 @@ static struct clk_rcg2 csi1phytimer_clk_src = { static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = { F(160000000, P_GPLL0, 5, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(228570000, P_GPLL0, 3.5, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), F(320000000, P_GPLL0, 2.5, 0, 0), F(465000000, P_GPLL2, 2, 0, 0), { } @@ -1290,6 +1294,8 @@ static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = { F(50000000, P_GPLL0_AUX, 16, 0, 0), F(80000000, P_GPLL0_AUX, 10, 0, 0), F(100000000, P_GPLL0_AUX, 8, 0, 0), + F(145500000, P_GPLL0_AUX, 5.5, 0, 0), + F(153600000, P_GPLL0, 4, 0, 0), F(160000000, P_GPLL0_AUX, 5, 0, 0), F(177780000, P_GPLL0_AUX, 4.5, 0, 0), F(200000000, P_GPLL0_AUX, 4, 0, 0), @@ -1462,7 +1468,9 @@ static struct clk_rcg2 bimc_gpu_clk_src = { }; static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { + F(57140000, P_GPLL0, 14, 0, 0), F(80000000, P_GPLL0, 10, 0, 0), + F(100000000, P_GPLL0, 8, 0, 0), { } }; @@ -1823,9 +1831,9 @@ static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = { }; static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = { - F(100000000, P_GPLL0, 8, 0, 0), - F(160000000, P_GPLL0, 5, 0, 0), - F(228570000, P_GPLL0, 3.5, 0, 0), + F(133330000, P_GPLL0, 6, 0, 0), + F(200000000, P_GPLL0, 4, 0, 0), + F(266670000, P_GPLL0, 3, 0, 0), { } }; diff --git a/drivers/extcon/extcon-qcom-spmi-misc.c b/drivers/extcon/extcon-qcom-spmi-misc.c index eb02cb962b5e..f72e90ceca53 100644 --- a/drivers/extcon/extcon-qcom-spmi-misc.c +++ b/drivers/extcon/extcon-qcom-spmi-misc.c @@ -123,7 +123,7 @@ static int qcom_usb_extcon_probe(struct platform_device *pdev) if (ret) return ret; - info->id_irq = platform_get_irq_byname(pdev, "usb_id"); + info->id_irq = platform_get_irq_byname_optional(pdev, "usb_id"); if (info->id_irq > 0) { ret = devm_request_threaded_irq(dev, info->id_irq, NULL, qcom_usb_irq_handler, @@ -136,7 +136,7 @@ static int qcom_usb_extcon_probe(struct platform_device *pdev) } } - info->vbus_irq = platform_get_irq_byname(pdev, "usb_vbus"); + info->vbus_irq = platform_get_irq_byname_optional(pdev, "usb_vbus"); if (info->vbus_irq > 0) { ret = devm_request_threaded_irq(dev, info->vbus_irq, NULL, qcom_usb_irq_handler, diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 38799effd00a..7fa03f524580 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -677,6 +677,14 @@ config DRM_PANEL_TRULY_NT35597_WQXGA Say Y here if you want to enable support for Truly NT35597 WQXGA Dual DSI Video Mode panel +config DRM_PANEL_TRULY_R65530 + tristate "Truly panel with R65530 driver IC" + depends on OF + depends on DRM_MIPI_DSI + help + Say Y here if you want to enable support for Truly DSI panel with + R65530 driver IC. + config DRM_PANEL_VISIONOX_RM69299 tristate "Visionox RM69299" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index 42a7ab54234b..09b20ae5870d 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_DRM_PANEL_TPO_TD028TTEC1) += panel-tpo-td028ttec1.o obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o +obj-$(CONFIG_DRM_PANEL_TRULY_R65530) += panel-truly-r63350.o obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o diff --git a/drivers/gpu/drm/panel/panel-truly-r63350.c b/drivers/gpu/drm/panel/panel-truly-r63350.c new file mode 100644 index 000000000000..f62e3dd74fea --- /dev/null +++ b/drivers/gpu/drm/panel/panel-truly-r63350.c @@ -0,0 +1,726 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_graph.h> +#include <linux/pinctrl/consumer.h> +#include <linux/regulator/consumer.h> + +#include <video/mipi_display.h> + +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_print.h> + +static const char * const regulator_names[] = { + "iovcc", + "avdd", + "avee", +}; + +enum panel_vendor { + NOT_INITIALIZE = -1, + TRULY, + AUO, +}; + +struct cmd_set { + const u8 *payload; + size_t size; + int wait_ms; +}; + +struct truly_data { + const struct cmd_set *panel_oncmds; + unsigned int num_oncmds; + const struct cmd_set *panel_offcmds; + unsigned int num_offcmds; +}; + +struct truly_panel { + struct drm_panel panel; + struct device *dev; + struct mipi_dsi_device *dsi; + const struct truly_data *data; + + struct regulator_bulk_data supplies[ARRAY_SIZE(regulator_names)]; + struct gpio_desc *reset_gpio; + + bool prepared; + bool enabled; +}; + +/* Panel vendor/type provided by bootloader */ +static enum panel_vendor vendor_from_bl = NOT_INITIALIZE; + +static int __init panel_setup(char *str) +{ + if (strstr(str, "truly_r63350")) + vendor_from_bl = TRULY; + else if (strstr(str, "auo_r63350")) + vendor_from_bl = AUO; + + return 1; +} +__setup("mdss_mdp.panel=", panel_setup); + +static inline struct truly_panel *panel_to_truly(struct drm_panel *panel) +{ + return container_of(panel, struct truly_panel, panel); +} + +static int truly_r63350_power_off(struct truly_panel *truly) +{ + gpiod_set_value(truly->reset_gpio, 1); + return regulator_bulk_disable(ARRAY_SIZE(truly->supplies), + truly->supplies); +} + +static int truly_r63350_power_on(struct truly_panel *truly) +{ + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(truly->supplies), + truly->supplies); + if (ret) + return ret; + + if (vendor_from_bl != NOT_INITIALIZE) { + /* + * If bootloader already configures the panel, we are + * done and skip panel reset below. + */ + return 0; + } + + /* Reset panel */ + gpiod_set_value(truly->reset_gpio, 0); + usleep_range(20000, 30000); + + gpiod_set_value(truly->reset_gpio, 1); + usleep_range(10000, 20000); + + gpiod_set_value(truly->reset_gpio, 0); + usleep_range(20000, 30000); + + return 0; +} + +static int truly_r63350_unprepare(struct drm_panel *panel) +{ + struct truly_panel *truly = panel_to_truly(panel); + const struct truly_data *data = truly->data; + const struct cmd_set *cmds = data->panel_offcmds; + unsigned int num_cmds = data->num_offcmds; + struct mipi_dsi_device *dsi = truly->dsi; + struct device *dev = truly->dev; + int ret; + int i; + + if (!truly->prepared) + return 0; + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0); + if (ret < 0) { + DRM_DEV_ERROR(dev, "set_display_off cmd failed: %d\n", ret); + return ret; + } + + /* 120ms delay required here as per DCS spec */ + msleep(120); + + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_ENTER_SLEEP_MODE, NULL, 0); + if (ret < 0) { + DRM_DEV_ERROR(dev, "enter_sleep cmd failed: %d\n", ret); + return ret; + } + + /* Panel-off magic commands */ + for (i = 0; i < num_cmds; i++) { + ret = mipi_dsi_dcs_write_buffer(dsi, cmds[i].payload, + cmds[i].size); + if (ret < 0) { + DRM_DEV_ERROR(dev, "off cmd tx%d failed: %d\n", i, ret); + return ret; + } + + if (cmds[i].wait_ms) + msleep(cmds[i].wait_ms); + else + usleep_range(80, 100); + } + + ret = truly_r63350_power_off(truly); + if (ret < 0) { + DRM_DEV_ERROR(dev, "power_off failed: %d\n", ret); + return ret; + } + + truly->prepared = false; + + return 0; +} + +static int truly_r63350_prepare(struct drm_panel *panel) +{ + struct truly_panel *truly = panel_to_truly(panel); + const struct truly_data *data = truly->data; + const struct cmd_set *cmds = data->panel_oncmds; + unsigned int num_cmds = data->num_oncmds; + struct mipi_dsi_device *dsi = truly->dsi; + struct device *dev = truly->dev; + int ret; + int i; + + if (truly->prepared) + return 0; + + ret = truly_r63350_power_on(truly); + if (ret < 0) { + DRM_DEV_ERROR(dev, "failed to power on: %d\n", ret); + return ret; + } + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + ret = mipi_dsi_dcs_soft_reset(dsi); + if (ret < 0) + return ret; + + usleep_range(10000, 20000); + + /* Panel-on magic commands */ + for (i = 0; i < num_cmds; i++) { + ret = mipi_dsi_dcs_write_buffer(dsi, cmds[i].payload, + cmds[i].size); + if (ret < 0) { + DRM_DEV_ERROR(dev, "on cmd tx%d failed: %d\n", i, ret); + goto power_off; + } + + if (cmds[i].wait_ms) + msleep(cmds[i].wait_ms); + else + usleep_range(80, 100); + } + + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0); + if (ret < 0) { + DRM_DEV_ERROR(dev, "exit_sleep_mode cmd failed: %d\n", ret); + goto power_off; + } + + /* Per DSI spec wait 120ms after sending exit sleep DCS command */ + msleep(120); + + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0); + if (ret < 0) { + DRM_DEV_ERROR(dev, "set_display_on cmd failed: %d\n", ret); + goto power_off; + } + + /* Per DSI spec wait 120ms after sending set_display_on DCS command */ + msleep(120); + + truly->prepared = true; + + return 0; + +power_off: + truly_r63350_power_off(truly); + return ret; +} + +static const struct drm_display_mode truly_fhd_mode = { + .clock = 144981, + .hdisplay = 1080, + .hsync_start = 1080 + 92, + .hsync_end = 1080 + 92 + 20, + .htotal = 1080 + 92 + 20 + 60, + .vdisplay = 1920, + .vsync_start = 1920 + 4, + .vsync_end = 1920 + 4 + 1, + .vtotal = 1920 + 4 + 1 + 5, + .flags = 0, +}; + +static int truly_r63350_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct truly_panel *truly = panel_to_truly(panel); + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, &truly_fhd_mode); + if (!mode) { + DRM_DEV_ERROR(truly->dev, + "failed to add display mode\n"); + return -ENOMEM; + } + + drm_mode_set_name(mode); + drm_mode_probed_add(connector, mode); + + connector->display_info.width_mm = 68; + connector->display_info.height_mm = 121; + + return 1; +} + +static const struct drm_panel_funcs truly_r63350_drm_funcs = { + .prepare = truly_r63350_prepare, + .unprepare = truly_r63350_unprepare, + .get_modes = truly_r63350_get_modes, +}; + +static int truly_r63350_panel_add(struct truly_panel *truly) +{ + struct device *dev = truly->dev; + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(truly->supplies); i++) + truly->supplies[i].supply = regulator_names[i]; + + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(truly->supplies), + truly->supplies); + if (ret) { + dev_err(dev, "failed to get regulator: %d\n", ret); + return ret; + } + + truly->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(truly->reset_gpio)) { + DRM_DEV_ERROR(dev, "failed to get reset gpio %ld\n", + PTR_ERR(truly->reset_gpio)); + return PTR_ERR(truly->reset_gpio); + } + + drm_panel_init(&truly->panel, dev, &truly_r63350_drm_funcs, + DRM_MODE_CONNECTOR_DSI); + + ret = drm_panel_of_backlight(&truly->panel); + if (ret) { + DRM_DEV_ERROR(dev, "failed to find backlight: %d\n", ret); + return ret; + } + + drm_panel_add(&truly->panel); + + return 0; +} + +static const u8 truly_oncmd0[] = { + 0xb0, 0x00, +}; + +static const u8 truly_oncmd1[] = { + 0xd6, 0x01, +}; + +static const u8 truly_oncmd2[] = { + 0xb3, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 truly_oncmd3[] = { + 0xb4, 0x0c, 0x00, +}; + +static const u8 truly_oncmd4[] = { + 0xb6, 0x4b, 0xdb, 0x16, +}; + +static const u8 truly_oncmd5[] = { + 0xbe, 0x00, 0x04, +}; + +static const u8 truly_oncmd6[] = { + 0xc0, 0x66, +}; + +static const u8 truly_oncmd7[] = { + 0xc1, 0x04, 0x60, 0x00, 0x20, 0xa9, 0x30, 0x20, + 0x63, 0xf0, 0xff, 0xff, 0x9b, 0x7b, 0xcf, 0xb5, + 0xff, 0xff, 0x87, 0x8c, 0x41, 0x22, 0x54, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x33, 0x03, + 0x22, 0x00, 0xff, +}; + +static const u8 truly_oncmd8[] = { + 0xc2, 0x31, 0xf7, 0x80, 0x06, 0x04, 0x00, 0x00, + 0x08, +}; + +static const u8 truly_oncmd9[] = { + 0xc3, 0x00, 0x00, 0x00, +}; + +static const u8 truly_oncmd10[] = { + 0xc4, 0x70, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, + 0x66, 0x66, 0x00, 0x02, +}; + +static const u8 truly_oncmd11[] = { + 0xc5, 0x00, +}; + +static const u8 truly_oncmd12[] = { + 0xc6, 0xc8, 0x3c, 0x3c, 0x07, 0x01, 0x07, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x1a, 0x07, 0xc8, +}; + +static const u8 truly_oncmd13[] = { + 0xc7, 0x03, 0x15, 0x1f, 0x2a, 0x39, 0x46, 0x4e, + 0x5b, 0x3d, 0x45, 0x52, 0x5f, 0x68, 0x6d, 0x72, + 0x01, 0x15, 0x1f, 0x2a, 0x39, 0x46, 0x4e, 0x5b, + 0x3d, 0x45, 0x52, 0x5f, 0x68, 0x6d, 0x78, +}; + +static const u8 truly_oncmd14[] = { + 0xcb, 0xff, 0xe1, 0x87, 0xff, 0x00, 0x00, 0x00, + 0x00, 0xff, 0xe1, 0x87, 0xff, 0xe8, 0x00, 0x00, +}; + +static const u8 truly_oncmd15[] = { + 0xcc, 0x34, +}; + +static const u8 truly_oncmd16[] = { + 0xd0, 0x11, 0x00, 0x00, 0x56, 0xd5, 0x40, 0x19, + 0x19, 0x09, 0x00, +}; + +static const u8 truly_oncmd17[] = { + 0xd1, 0x00, 0x48, 0x16, 0x0f, +}; + +static const u8 truly_oncmd18[] = { + 0xd2, 0x5c, 0x00, 0x00, +}; + +static const u8 truly_oncmd19[] = { + 0xd3, 0x1b, 0x33, 0xbb, 0xbb, 0xb3, 0x33, 0x33, + 0x33, 0x33, 0x00, 0x01, 0x00, 0x00, 0xd8, 0xa0, + 0x0c, 0x4d, 0x4d, 0x33, 0x33, 0x72, 0x12, 0x8a, + 0x57, 0x3d, 0xbc, +}; + +static const u8 truly_oncmd20[] = { + 0xd5, 0x06, 0x00, 0x00, 0x01, 0x39, 0x01, 0x39, +}; + +static const u8 truly_oncmd21[] = { + 0xd8, 0x00, 0x00, 0x00, +}; + +static const u8 truly_oncmd22[] = { + 0xd9, 0x00, 0x00, 0x00, +}; + +static const u8 truly_oncmd23[] = { + 0xfd, 0x00, 0x00, 0x00, 0x30, +}; + +static const u8 truly_oncmd24[] = { + 0x35, 0x00, +}; + +static const u8 truly_oncmd25[] = { + 0x29, +}; + +static const u8 truly_oncmd26[] = { + 0x11, +}; + +static const struct cmd_set truly_oncmds[] = { + { truly_oncmd0, ARRAY_SIZE(truly_oncmd0), }, + { truly_oncmd1, ARRAY_SIZE(truly_oncmd1), }, + { truly_oncmd2, ARRAY_SIZE(truly_oncmd2), }, + { truly_oncmd3, ARRAY_SIZE(truly_oncmd3), }, + { truly_oncmd4, ARRAY_SIZE(truly_oncmd4), }, + { truly_oncmd5, ARRAY_SIZE(truly_oncmd5), }, + { truly_oncmd6, ARRAY_SIZE(truly_oncmd6), }, + { truly_oncmd7, ARRAY_SIZE(truly_oncmd7), }, + { truly_oncmd8, ARRAY_SIZE(truly_oncmd8), }, + { truly_oncmd9, ARRAY_SIZE(truly_oncmd9), }, + { truly_oncmd10, ARRAY_SIZE(truly_oncmd10), }, + { truly_oncmd11, ARRAY_SIZE(truly_oncmd11), }, + { truly_oncmd12, ARRAY_SIZE(truly_oncmd12), }, + { truly_oncmd13, ARRAY_SIZE(truly_oncmd13), }, + { truly_oncmd14, ARRAY_SIZE(truly_oncmd14), }, + { truly_oncmd15, ARRAY_SIZE(truly_oncmd15), }, + { truly_oncmd16, ARRAY_SIZE(truly_oncmd16), }, + { truly_oncmd17, ARRAY_SIZE(truly_oncmd17), }, + { truly_oncmd18, ARRAY_SIZE(truly_oncmd18), }, + { truly_oncmd19, ARRAY_SIZE(truly_oncmd19), }, + { truly_oncmd20, ARRAY_SIZE(truly_oncmd20), }, + { truly_oncmd21, ARRAY_SIZE(truly_oncmd21), }, + { truly_oncmd22, ARRAY_SIZE(truly_oncmd22), }, + { truly_oncmd23, ARRAY_SIZE(truly_oncmd23), }, + { truly_oncmd24, ARRAY_SIZE(truly_oncmd24), }, + { truly_oncmd25, ARRAY_SIZE(truly_oncmd25), 50, }, + { truly_oncmd26, ARRAY_SIZE(truly_oncmd26), 120, }, +}; + +static const u8 truly_offcmd0[] = { + 0x28, +}; + +static const u8 truly_offcmd1[] = { + 0xb0, 0x04, +}; + +static const u8 truly_offcmd2[] = { + 0xd3, 0x13, 0x33, 0xbb, 0xb3, 0xb3, 0x33, 0x33, + 0x33, 0x33, 0x00, 0x01, 0x00, 0x00, 0xd8, 0xa0, + 0x0c, 0x4d, 0x4d, 0x33, 0x33, 0x72, 0x12, 0x8a, + 0x57, 0x3d, 0xbc, +}; + +static const u8 truly_offcmd3[] = { + 0x10, +}; + +static const u8 truly_offcmd4[] = { + 0xb0, 0x00, +}; + +static const u8 truly_offcmd5[] = { + 0xb1, 0x01, +}; + +static const struct cmd_set truly_offcmds[] = { + { truly_offcmd0, ARRAY_SIZE(truly_offcmd0), 20, }, + { truly_offcmd1, ARRAY_SIZE(truly_offcmd1), }, + { truly_offcmd2, ARRAY_SIZE(truly_offcmd2), 27, }, + { truly_offcmd3, ARRAY_SIZE(truly_offcmd3), 120, }, + { truly_offcmd4, ARRAY_SIZE(truly_offcmd4), }, + { truly_offcmd5, ARRAY_SIZE(truly_offcmd5), }, +}; + +static const struct truly_data truly_fhd_data = { + .panel_oncmds = truly_oncmds, + .num_oncmds = ARRAY_SIZE(truly_oncmds), + .panel_offcmds = truly_offcmds, + .num_offcmds = ARRAY_SIZE(truly_offcmds), +}; + +static const u8 auo_oncmd0[] = { + 0xb0, 0x04, +}; + +static const u8 auo_oncmd1[] = { + 0xd6, 0x01, +}; + +static const u8 auo_oncmd2[] = { + 0xb3, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static const u8 auo_oncmd3[] = { + 0xb4, 0x0c, 0x00, +}; + +static const u8 auo_oncmd4[] = { + 0xb6, 0x4b, 0xdb, 0x00, +}; + +static const u8 auo_oncmd5[] = { + 0xc0, 0x66, +}; + +static const u8 auo_oncmd6[] = { + 0xc1, 0x04, 0x60, 0x00, 0x20, 0x29, 0x41, 0x22, + 0xfb, 0xf0, 0xff, 0xff, 0x9b, 0x7b, 0xcf, 0xb5, + 0xff, 0xff, 0x87, 0x8c, 0xc5, 0x11, 0x54, 0x02, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x11, 0x02, + 0x21, 0x00, 0xff, 0x11, +}; + +static const u8 auo_oncmd7[] = { + 0xc2, 0x31, 0xf7, 0x80, 0x06, 0x04, 0x00, 0x00, + 0x08, +}; + +static const u8 auo_oncmd8[] = { + 0xc4, 0x70, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, + 0x66, 0x66, 0x00, 0x02, +}; + +static const u8 auo_oncmd9[] = { + 0xc6, 0xc8, 0x3c, 0x3c, 0x07, 0x01, 0x07, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0e, 0x1a, 0x07, 0xc8, +}; + +static const u8 auo_oncmd10[] = { + 0xc7, 0x0a, 0x18, 0x20, 0x29, 0x37, 0x43, 0x4d, + 0x5b, 0x3f, 0x46, 0x52, 0x5f, 0x67, 0x70, 0x7c, + 0x0a, 0x18, 0x20, 0x29, 0x37, 0x43, 0x4d, 0x5b, + 0x3f, 0x46, 0x52, 0x5f, 0x67, 0x70, 0x7c, +}; + +static const u8 auo_oncmd11[] = { + 0xcb, 0x7f, 0xe1, 0x87, 0xff, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, +}; + +static const u8 auo_oncmd12[] = { + 0xcc, 0x32, +}; + +static const u8 auo_oncmd13[] = { + 0xd0, 0x11, 0x00, 0x00, 0x56, 0xd7, 0x40, 0x19, + 0x19, 0x09, 0x00, +}; + +static const u8 auo_oncmd14[] = { + 0xd1, 0x00, 0x48, 0x16, 0x0f, +}; + +static const u8 auo_oncmd15[] = { + 0xd3, 0x1b, 0x33, 0xbb, 0xbb, 0xb3, 0x33, 0x33, + 0x33, 0x33, 0x00, 0x01, 0x00, 0x00, 0xd8, 0xa0, + 0x0c, 0x37, 0x37, 0x33, 0x33, 0x72, 0x12, 0x8a, + 0x57, 0x3d, 0xbc, +}; + +static const u8 auo_oncmd16[] = { + 0xd5, 0x06, 0x00, 0x00, 0x01, 0x35, 0x01, 0x35, +}; + +static const u8 auo_oncmd17[] = { + 0x29, +}; + +static const u8 auo_oncmd18[] = { + 0x11, +}; + +static const struct cmd_set auo_oncmds[] = { + { auo_oncmd0, ARRAY_SIZE(auo_oncmd0), }, + { auo_oncmd1, ARRAY_SIZE(auo_oncmd1), }, + { auo_oncmd2, ARRAY_SIZE(auo_oncmd2), }, + { auo_oncmd3, ARRAY_SIZE(auo_oncmd3), }, + { auo_oncmd4, ARRAY_SIZE(auo_oncmd4), }, + { auo_oncmd5, ARRAY_SIZE(auo_oncmd5), }, + { auo_oncmd6, ARRAY_SIZE(auo_oncmd6), }, + { auo_oncmd7, ARRAY_SIZE(auo_oncmd7), }, + { auo_oncmd8, ARRAY_SIZE(auo_oncmd8), }, + { auo_oncmd9, ARRAY_SIZE(auo_oncmd9), }, + { auo_oncmd10, ARRAY_SIZE(auo_oncmd10), }, + { auo_oncmd11, ARRAY_SIZE(auo_oncmd11), }, + { auo_oncmd12, ARRAY_SIZE(auo_oncmd12), }, + { auo_oncmd13, ARRAY_SIZE(auo_oncmd13), }, + { auo_oncmd14, ARRAY_SIZE(auo_oncmd14), }, + { auo_oncmd15, ARRAY_SIZE(auo_oncmd15), }, + { auo_oncmd16, ARRAY_SIZE(auo_oncmd16), }, + { auo_oncmd17, ARRAY_SIZE(auo_oncmd17), 100, }, + { auo_oncmd18, ARRAY_SIZE(auo_oncmd18), 120, }, +}; + +static const u8 auo_offcmd0[] = { + 0x28, +}; + +static const u8 auo_offcmd1[] = { + 0xb0, 0x04, +}; + +static const struct cmd_set auo_offcmds[] = { + { auo_offcmd0, ARRAY_SIZE(auo_offcmd0), 10, }, + { auo_offcmd1, ARRAY_SIZE(auo_offcmd1), 120, }, +}; + +static const struct truly_data auo_fhd_data = { + .panel_oncmds = auo_oncmds, + .num_oncmds = ARRAY_SIZE(auo_oncmds), + .panel_offcmds = auo_offcmds, + .num_offcmds = ARRAY_SIZE(auo_offcmds), +}; + +static int truly_r63350_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct truly_panel *truly; + int ret; + + truly = devm_kzalloc(dev, sizeof(*truly), GFP_KERNEL); + if (!truly) + return -ENOMEM; + + truly->data = of_device_get_match_data(dev); + if (!truly->data) + return -ENODEV; + + /* Override data if bootloader provides the panel type */ + if (vendor_from_bl == TRULY) + truly->data = &truly_fhd_data; + else if (vendor_from_bl == AUO) + truly->data = &auo_fhd_data; + + truly->dev = dev; + + ret = truly_r63350_panel_add(truly); + if (ret) + return ret; + + dsi->lanes = 4; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM; + truly->dsi = dsi; + + ret = mipi_dsi_attach(dsi); + if (ret) { + DRM_DEV_ERROR(dev, "failed to attach DSI device: %d\n", ret); + goto rm_panel; + } + + mipi_dsi_set_drvdata(dsi, truly); + + return 0; + +rm_panel: + drm_panel_remove(&truly->panel); + return ret; +} + +static int truly_r63350_remove(struct mipi_dsi_device *dsi) +{ + struct truly_panel *truly = mipi_dsi_get_drvdata(dsi); + + mipi_dsi_detach(truly->dsi); + drm_panel_remove(&truly->panel); + + return 0; +} + +static const struct of_device_id truly_r63350_of_match[] = { + { .compatible = "truly,r63350-fhd", .data = &truly_fhd_data, }, + { .compatible = "auo,r63350-fhd", .data = &auo_fhd_data, }, + { } +}; +MODULE_DEVICE_TABLE(of, truly_r63350_of_match); + +static struct mipi_dsi_driver truly_r63350_driver = { + .driver = { + .name = "panel-truly-r63350", + .of_match_table = truly_r63350_of_match, + }, + .probe = truly_r63350_probe, + .remove = truly_r63350_remove, +}; +module_mipi_dsi_driver(truly_r63350_driver); + +MODULE_DESCRIPTION("Truly R63350 DSI Panel Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index fb013191c29b..7e8bcbb2f5db 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -233,10 +233,30 @@ static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) return ret; } +static int __qcom_icc_set(struct icc_node *n, struct qcom_icc_node *qn, + u64 sum_bw) +{ + int ret; + + if (!qn->qos.ap_owned) { + /* send bandwidth request message to the RPM processor */ + ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); + if (ret) + return ret; + } else if (qn->qos.qos_mode != -1) { + /* set bandwidth directly from the AP */ + ret = qcom_icc_qos_set(n, sum_bw); + if (ret) + return ret; + } + + return 0; +} + static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) { struct qcom_icc_provider *qp; - struct qcom_icc_node *qn; + struct qcom_icc_node *src_qn = NULL, *dst_qn = NULL; struct icc_provider *provider; struct icc_node *n; u64 sum_bw; @@ -246,7 +266,9 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) u32 agg_peak = 0; int ret, i; - qn = src->data; + src_qn = src->data; + if (dst) + dst_qn = dst->data; provider = src->provider; qp = to_qcom_provider(provider); @@ -257,21 +279,18 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) sum_bw = icc_units_to_bps(agg_avg); max_peak_bw = icc_units_to_bps(agg_peak); - if (!qn->qos.ap_owned) { - /* send bandwidth request message to the RPM processor */ - ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); - if (ret) - return ret; - } else if (qn->qos.qos_mode != -1) { - /* set bandwidth directly from the AP */ - ret = qcom_icc_qos_set(src, sum_bw); + ret = __qcom_icc_set(src, src_qn, sum_bw); + if (ret) + return ret; + if (dst_qn) { + ret = __qcom_icc_set(dst, dst_qn, sum_bw); if (ret) return ret; } rate = max(sum_bw, max_peak_bw); - do_div(rate, qn->buswidth); + do_div(rate, src_qn->buswidth); rate = min_t(u64, rate, LONG_MAX); for (i = 0; i < qp->num_clks; i++) { diff --git a/drivers/media/platform/qcom/venus/core.c b/drivers/media/platform/qcom/venus/core.c index 877eca125803..e113b05b6717 100644 --- a/drivers/media/platform/qcom/venus/core.c +++ b/drivers/media/platform/qcom/venus/core.c @@ -540,6 +540,62 @@ static const struct venus_resources msm8916_res = { .fwname = "qcom/venus-1.8/venus.mdt", }; +static const struct freq_tbl msm8939_freq_table[] = { + { 489600, 266670000 }, /* HEVC 1080p 60fps */ + { 244800, 133330000 }, /* HEVC 1080p 30fps */ + { 220800, 133330000 }, /* HEVC 720p 60fps */ + { 108000, 133330000 }, /* HEVC 720p 30fps */ + { 72000, 133330000 }, /* HEVC VGA 60fps */ + { 36000, 133330000 }, /* HEVC VGA 30 fps */ +}; + +static const struct reg_val msm8939_reg_preset[] = { + { 0xe0020, 0x0aaaaaaa }, + { 0xe0024, 0x0aaaaaaa }, + { 0x80124, 0x00000003 }, +}; + +static const struct bw_tbl msm8939_bw_table_enc[] = { + { 1387725, 2577408, 0, 0, 0 }, /* HEVC 1080p 60fps */ + { 693863, 644403, 0, 0, 0 }, /* HEVC 1080p 30fps */ + { 612250, 1288704, 0, 0, 0 }, /* HEVC 720p 60fps */ + { 306074, 644403, 0, 0, 0 }, /* HEVC 720p 30fps */ + { 204083, 1288704, 0, 0, 0 }, /* HEVC VGA 60fps */ + { 101991, 644403, 0, 0, 0 }, /* HEVC VGA 30 fps */ +}; + +static const struct bw_tbl msm8939_bw_table_dec[] = { + { 1306624, 2291405, 0, 0, 0 }, /* HEVC 1080p 60fps */ + { 653312, 572826, 0, 0, 0 }, /* HEVC 1080p 30fps */ + { 576410, 1145754, 0, 0, 0 }, /* HEVC 720p 60fps */ + { 288256, 572826, 0, 0, 0 }, /* HEVC 720p 30fps */ + { 192103, 1145754, 0, 0, 0 }, /* HEVC VGA 60fps */ + { 96051, 572826, 0, 0, 0 }, /* HEVC VGA 30 fps */ +}; + +static const struct venus_resources msm8939_res = { + .freq_tbl = msm8939_freq_table, + .freq_tbl_size = ARRAY_SIZE(msm8939_freq_table), + .reg_tbl = msm8939_reg_preset, + .reg_tbl_size = ARRAY_SIZE(msm8939_reg_preset), + .bw_tbl_enc = msm8939_bw_table_enc, + .bw_tbl_enc_size = ARRAY_SIZE(msm8939_bw_table_enc), + .bw_tbl_dec = msm8939_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(msm8939_bw_table_dec), + .clks = { "core", "iface", "bus", }, + .clks_num = 3, + .vcodec0_clks = { "vcodec0_core" }, + .vcodec1_clks = { "vcodec1_core" }, + .vcodec_clks_num = 1, + .max_load = 489600, /* 1080p @ 30 + 1080p @ 30 */ + .hfi_version = HFI_VERSION_1XX, + .vmem_id = VIDC_RESOURCE_NONE, + .vmem_size = 0, + .vmem_addr = 0, + .dma_mask = 0xddc00000 - 1, + .fwname = "qcom/venus-1.8/venus.mdt", +}; + static const struct freq_tbl msm8996_freq_table[] = { { 1944000, 520000000 }, /* 4k UHD @ 60 (decode only) */ { 972000, 520000000 }, /* 4k UHD @ 30 */ @@ -860,6 +916,7 @@ static const struct venus_resources sc7280_res = { static const struct of_device_id venus_dt_match[] = { { .compatible = "qcom,msm8916-venus", .data = &msm8916_res, }, + { .compatible = "qcom,msm8939-venus", .data = &msm8939_res, }, { .compatible = "qcom,msm8996-venus", .data = &msm8996_res, }, { .compatible = "qcom,sdm660-venus", .data = &sdm660_res, }, { .compatible = "qcom,sdm845-venus", .data = &sdm845_res, }, diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c b/drivers/media/platform/qcom/venus/pm_helpers.c index cb48c5ff3dee..480b6311c106 100644 --- a/drivers/media/platform/qcom/venus/pm_helpers.c +++ b/drivers/media/platform/qcom/venus/pm_helpers.c @@ -322,10 +322,55 @@ static int core_power_v1(struct venus_core *core, int on) return ret; } +static int vdec_get_v1(struct device *dev) +{ + struct venus_core *core = dev_get_drvdata(dev); + + return vcodec_clks_get(core, dev, core->vcodec0_clks, + core->res->vcodec0_clks); +} + +static int vdec_power_v1(struct device *dev, int on) +{ + struct venus_core *core = dev_get_drvdata(dev); + int ret = 0; + + if (on == POWER_ON) + ret = vcodec_clks_enable(core, core->vcodec0_clks); + else + vcodec_clks_disable(core, core->vcodec0_clks); + + return ret; +} + +static int venc_get_v1(struct device *dev) +{ + struct venus_core *core = dev_get_drvdata(dev); + + return vcodec_clks_get(core, dev, core->vcodec1_clks, + core->res->vcodec1_clks); +} + +static int venc_power_v1(struct device *dev, int on) +{ + struct venus_core *core = dev_get_drvdata(dev); + int ret = 0; + + if (on == POWER_ON) + ret = vcodec_clks_enable(core, core->vcodec1_clks); + else + vcodec_clks_disable(core, core->vcodec1_clks); + + return ret; +} static const struct venus_pm_ops pm_ops_v1 = { .core_get = core_get_v1, .core_put = core_put_v1, .core_power = core_power_v1, + .vdec_get = vdec_get_v1, + .vdec_power = vdec_power_v1, + .venc_get = venc_get_v1, + .venc_power = venc_power_v1, .load_scale = load_scale_v1, }; diff --git a/drivers/net/wireless/ath/wcn36xx/Makefile b/drivers/net/wireless/ath/wcn36xx/Makefile index 27413703ad69..26bec795b372 100644 --- a/drivers/net/wireless/ath/wcn36xx/Makefile +++ b/drivers/net/wireless/ath/wcn36xx/Makefile @@ -5,6 +5,7 @@ wcn36xx-y += main.o \ txrx.o \ smd.o \ pmc.o \ - debug.o + debug.o \ + firmware.o wcn36xx-$(CONFIG_NL80211_TESTMODE) += testmode.o diff --git a/drivers/net/wireless/ath/wcn36xx/debug.c b/drivers/net/wireless/ath/wcn36xx/debug.c index 6af306ae41ad..ca6f22a00f75 100644 --- a/drivers/net/wireless/ath/wcn36xx/debug.c +++ b/drivers/net/wireless/ath/wcn36xx/debug.c @@ -21,6 +21,7 @@ #include "wcn36xx.h" #include "debug.h" #include "pmc.h" +#include "firmware.h" #ifdef CONFIG_WCN36XX_DEBUGFS @@ -136,6 +137,40 @@ static const struct file_operations fops_wcn36xx_dump = { .write = write_file_dump, }; +static ssize_t read_file_firmware_feature_caps(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct wcn36xx *wcn = file->private_data; + unsigned long page = get_zeroed_page(GFP_KERNEL); + char *p = (char *)page; + int i; + int ret; + + if (!p) + return -ENOMEM; + + mutex_lock(&wcn->hal_mutex); + for (i = 0; i < MAX_FEATURE_SUPPORTED; i++) { + if (wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, i)) { + p += sprintf(p, "FW Cap = %s\n", + wcn36xx_firmware_get_cap_name(i)); + } + } + mutex_unlock(&wcn->hal_mutex); + + ret = simple_read_from_buffer(user_buf, count, ppos, (char *)page, + (unsigned long)p - page); + + free_page(page); + return ret; +} + +static const struct file_operations fops_wcn36xx_firmware_feat_caps = { + .open = simple_open, + .read = read_file_firmware_feature_caps, +}; + #define ADD_FILE(name, mode, fop, priv_data) \ do { \ struct dentry *d; \ @@ -163,6 +198,8 @@ void wcn36xx_debugfs_init(struct wcn36xx *wcn) ADD_FILE(bmps_switcher, 0600, &fops_wcn36xx_bmps, wcn); ADD_FILE(dump, 0200, &fops_wcn36xx_dump, wcn); + ADD_FILE(firmware_feat_caps, 0200, + &fops_wcn36xx_firmware_feat_caps, wcn); } void wcn36xx_debugfs_exit(struct wcn36xx *wcn) diff --git a/drivers/net/wireless/ath/wcn36xx/debug.h b/drivers/net/wireless/ath/wcn36xx/debug.h index 46307aa562d3..7116d96e0543 100644 --- a/drivers/net/wireless/ath/wcn36xx/debug.h +++ b/drivers/net/wireless/ath/wcn36xx/debug.h @@ -31,6 +31,7 @@ struct wcn36xx_dfs_entry { struct dentry *rootdir; struct wcn36xx_dfs_file file_bmps_switcher; struct wcn36xx_dfs_file file_dump; + struct wcn36xx_dfs_file file_firmware_feat_caps; }; void wcn36xx_debugfs_init(struct wcn36xx *wcn); diff --git a/drivers/net/wireless/ath/wcn36xx/firmware.c b/drivers/net/wireless/ath/wcn36xx/firmware.c new file mode 100644 index 000000000000..4b7f439e4db5 --- /dev/null +++ b/drivers/net/wireless/ath/wcn36xx/firmware.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "wcn36xx.h" +#include "firmware.h" + +#define DEFINE(s)[s] = #s + +static const char * const wcn36xx_firmware_caps_names[] = { + DEFINE(MCC), + DEFINE(P2P), + DEFINE(DOT11AC), + DEFINE(SLM_SESSIONIZATION), + DEFINE(DOT11AC_OPMODE), + DEFINE(SAP32STA), + DEFINE(TDLS), + DEFINE(P2P_GO_NOA_DECOUPLE_INIT_SCAN), + DEFINE(WLANACTIVE_OFFLOAD), + DEFINE(BEACON_OFFLOAD), + DEFINE(SCAN_OFFLOAD), + DEFINE(ROAM_OFFLOAD), + DEFINE(BCN_MISS_OFFLOAD), + DEFINE(STA_POWERSAVE), + DEFINE(STA_ADVANCED_PWRSAVE), + DEFINE(AP_UAPSD), + DEFINE(AP_DFS), + DEFINE(BLOCKACK), + DEFINE(PHY_ERR), + DEFINE(BCN_FILTER), + DEFINE(RTT), + DEFINE(RATECTRL), + DEFINE(WOW), + DEFINE(WLAN_ROAM_SCAN_OFFLOAD), + DEFINE(SPECULATIVE_PS_POLL), + DEFINE(SCAN_SCH), + DEFINE(IBSS_HEARTBEAT_OFFLOAD), + DEFINE(WLAN_SCAN_OFFLOAD), + DEFINE(WLAN_PERIODIC_TX_PTRN), + DEFINE(ADVANCE_TDLS), + DEFINE(BATCH_SCAN), + DEFINE(FW_IN_TX_PATH), + DEFINE(EXTENDED_NSOFFLOAD_SLOT), + DEFINE(CH_SWITCH_V1), + DEFINE(HT40_OBSS_SCAN), + DEFINE(UPDATE_CHANNEL_LIST), + DEFINE(WLAN_MCADDR_FLT), + DEFINE(WLAN_CH144), + DEFINE(NAN), + DEFINE(TDLS_SCAN_COEXISTENCE), + DEFINE(LINK_LAYER_STATS_MEAS), + DEFINE(MU_MIMO), + DEFINE(EXTENDED_SCAN), + DEFINE(DYNAMIC_WMM_PS), + DEFINE(MAC_SPOOFED_SCAN), + DEFINE(BMU_ERROR_GENERIC_RECOVERY), + DEFINE(DISA), + DEFINE(FW_STATS), + DEFINE(WPS_PRBRSP_TMPL), + DEFINE(BCN_IE_FLT_DELTA), + DEFINE(TDLS_OFF_CHANNEL), + DEFINE(RTT3), + DEFINE(MGMT_FRAME_LOGGING), + DEFINE(ENHANCED_TXBD_COMPLETION), + DEFINE(LOGGING_ENHANCEMENT), + DEFINE(EXT_SCAN_ENHANCED), + DEFINE(MEMORY_DUMP_SUPPORTED), + DEFINE(PER_PKT_STATS_SUPPORTED), + DEFINE(EXT_LL_STAT), + DEFINE(WIFI_CONFIG), + DEFINE(ANTENNA_DIVERSITY_SELECTION), +}; + +#undef DEFINE + +const char *wcn36xx_firmware_get_cap_name(enum wcn36xx_firmware_feat_caps x) +{ + if (x >= ARRAY_SIZE(wcn36xx_firmware_caps_names)) + return "UNKNOWN"; + return wcn36xx_firmware_caps_names[x]; +} + +void wcn36xx_firmware_set_feat_caps(u32 *bitmap, + enum wcn36xx_firmware_feat_caps cap) +{ + int arr_idx, bit_idx; + + if (cap < 0 || cap > 127) { + wcn36xx_warn("error cap idx %d\n", cap); + return; + } + + arr_idx = cap / 32; + bit_idx = cap % 32; + bitmap[arr_idx] |= (1 << bit_idx); +} + +int wcn36xx_firmware_get_feat_caps(u32 *bitmap, + enum wcn36xx_firmware_feat_caps cap) +{ + int arr_idx, bit_idx; + + if (cap < 0 || cap > 127) { + wcn36xx_warn("error cap idx %d\n", cap); + return -EINVAL; + } + + arr_idx = cap / 32; + bit_idx = cap % 32; + + return (bitmap[arr_idx] & (1 << bit_idx)) ? 1 : 0; +} + +void wcn36xx_firmware_clear_feat_caps(u32 *bitmap, + enum wcn36xx_firmware_feat_caps cap) +{ + int arr_idx, bit_idx; + + if (cap < 0 || cap > 127) { + wcn36xx_warn("error cap idx %d\n", cap); + return; + } + + arr_idx = cap / 32; + bit_idx = cap % 32; + bitmap[arr_idx] &= ~(1 << bit_idx); +} diff --git a/drivers/net/wireless/ath/wcn36xx/firmware.h b/drivers/net/wireless/ath/wcn36xx/firmware.h new file mode 100644 index 000000000000..f991cf959f82 --- /dev/null +++ b/drivers/net/wireless/ath/wcn36xx/firmware.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _FIRMWARE_H_ +#define _FIRMWARE_H_ + +/* Capability bitmap exchange definitions and macros starts */ + +enum wcn36xx_firmware_feat_caps { + MCC = 0, + P2P = 1, + DOT11AC = 2, + SLM_SESSIONIZATION = 3, + DOT11AC_OPMODE = 4, + SAP32STA = 5, + TDLS = 6, + P2P_GO_NOA_DECOUPLE_INIT_SCAN = 7, + WLANACTIVE_OFFLOAD = 8, + BEACON_OFFLOAD = 9, + SCAN_OFFLOAD = 10, + ROAM_OFFLOAD = 11, + BCN_MISS_OFFLOAD = 12, + STA_POWERSAVE = 13, + STA_ADVANCED_PWRSAVE = 14, + AP_UAPSD = 15, + AP_DFS = 16, + BLOCKACK = 17, + PHY_ERR = 18, + BCN_FILTER = 19, + RTT = 20, + RATECTRL = 21, + WOW = 22, + WLAN_ROAM_SCAN_OFFLOAD = 23, + SPECULATIVE_PS_POLL = 24, + SCAN_SCH = 25, + IBSS_HEARTBEAT_OFFLOAD = 26, + WLAN_SCAN_OFFLOAD = 27, + WLAN_PERIODIC_TX_PTRN = 28, + ADVANCE_TDLS = 29, + BATCH_SCAN = 30, + FW_IN_TX_PATH = 31, + EXTENDED_NSOFFLOAD_SLOT = 32, + CH_SWITCH_V1 = 33, + HT40_OBSS_SCAN = 34, + UPDATE_CHANNEL_LIST = 35, + WLAN_MCADDR_FLT = 36, + WLAN_CH144 = 37, + NAN = 38, + TDLS_SCAN_COEXISTENCE = 39, + LINK_LAYER_STATS_MEAS = 40, + MU_MIMO = 41, + EXTENDED_SCAN = 42, + DYNAMIC_WMM_PS = 43, + MAC_SPOOFED_SCAN = 44, + BMU_ERROR_GENERIC_RECOVERY = 45, + DISA = 46, + FW_STATS = 47, + WPS_PRBRSP_TMPL = 48, + BCN_IE_FLT_DELTA = 49, + TDLS_OFF_CHANNEL = 51, + RTT3 = 52, + MGMT_FRAME_LOGGING = 53, + ENHANCED_TXBD_COMPLETION = 54, + LOGGING_ENHANCEMENT = 55, + EXT_SCAN_ENHANCED = 56, + MEMORY_DUMP_SUPPORTED = 57, + PER_PKT_STATS_SUPPORTED = 58, + EXT_LL_STAT = 60, + WIFI_CONFIG = 61, + ANTENNA_DIVERSITY_SELECTION = 62, + + MAX_FEATURE_SUPPORTED = 128, +}; + +void wcn36xx_firmware_set_feat_caps(u32 *bitmap, + enum wcn36xx_firmware_feat_caps cap); +int wcn36xx_firmware_get_feat_caps(u32 *bitmap, + enum wcn36xx_firmware_feat_caps cap); +void wcn36xx_firmware_clear_feat_caps(u32 *bitmap, + enum wcn36xx_firmware_feat_caps cap); + +const char *wcn36xx_firmware_get_cap_name(enum wcn36xx_firmware_feat_caps x); + +#endif /* _FIRMWARE_H_ */ + diff --git a/drivers/net/wireless/ath/wcn36xx/hal.h b/drivers/net/wireless/ath/wcn36xx/hal.h index 46a49f0a51b3..5c45b23c7880 100644 --- a/drivers/net/wireless/ath/wcn36xx/hal.h +++ b/drivers/net/wireless/ath/wcn36xx/hal.h @@ -4758,74 +4758,6 @@ struct wcn36xx_hal_set_power_params_resp { u32 status; } __packed; -/* Capability bitmap exchange definitions and macros starts */ - -enum place_holder_in_cap_bitmap { - MCC = 0, - P2P = 1, - DOT11AC = 2, - SLM_SESSIONIZATION = 3, - DOT11AC_OPMODE = 4, - SAP32STA = 5, - TDLS = 6, - P2P_GO_NOA_DECOUPLE_INIT_SCAN = 7, - WLANACTIVE_OFFLOAD = 8, - BEACON_OFFLOAD = 9, - SCAN_OFFLOAD = 10, - ROAM_OFFLOAD = 11, - BCN_MISS_OFFLOAD = 12, - STA_POWERSAVE = 13, - STA_ADVANCED_PWRSAVE = 14, - AP_UAPSD = 15, - AP_DFS = 16, - BLOCKACK = 17, - PHY_ERR = 18, - BCN_FILTER = 19, - RTT = 20, - RATECTRL = 21, - WOW = 22, - WLAN_ROAM_SCAN_OFFLOAD = 23, - SPECULATIVE_PS_POLL = 24, - SCAN_SCH = 25, - IBSS_HEARTBEAT_OFFLOAD = 26, - WLAN_SCAN_OFFLOAD = 27, - WLAN_PERIODIC_TX_PTRN = 28, - ADVANCE_TDLS = 29, - BATCH_SCAN = 30, - FW_IN_TX_PATH = 31, - EXTENDED_NSOFFLOAD_SLOT = 32, - CH_SWITCH_V1 = 33, - HT40_OBSS_SCAN = 34, - UPDATE_CHANNEL_LIST = 35, - WLAN_MCADDR_FLT = 36, - WLAN_CH144 = 37, - NAN = 38, - TDLS_SCAN_COEXISTENCE = 39, - LINK_LAYER_STATS_MEAS = 40, - MU_MIMO = 41, - EXTENDED_SCAN = 42, - DYNAMIC_WMM_PS = 43, - MAC_SPOOFED_SCAN = 44, - BMU_ERROR_GENERIC_RECOVERY = 45, - DISA = 46, - FW_STATS = 47, - WPS_PRBRSP_TMPL = 48, - BCN_IE_FLT_DELTA = 49, - TDLS_OFF_CHANNEL = 51, - RTT3 = 52, - MGMT_FRAME_LOGGING = 53, - ENHANCED_TXBD_COMPLETION = 54, - LOGGING_ENHANCEMENT = 55, - EXT_SCAN_ENHANCED = 56, - MEMORY_DUMP_SUPPORTED = 57, - PER_PKT_STATS_SUPPORTED = 58, - EXT_LL_STAT = 60, - WIFI_CONFIG = 61, - ANTENNA_DIVERSITY_SELECTION = 62, - - MAX_FEATURE_SUPPORTED = 128, -}; - #define WCN36XX_HAL_CAPS_SIZE 4 struct wcn36xx_hal_feat_caps_msg { diff --git a/drivers/net/wireless/ath/wcn36xx/main.c b/drivers/net/wireless/ath/wcn36xx/main.c index e34d3d0b7082..fec85e89a02f 100644 --- a/drivers/net/wireless/ath/wcn36xx/main.c +++ b/drivers/net/wireless/ath/wcn36xx/main.c @@ -28,6 +28,7 @@ #include <net/ipv6.h> #include "wcn36xx.h" #include "testmode.h" +#include "firmware.h" unsigned int wcn36xx_dbg_mask; module_param_named(debug_mask, wcn36xx_dbg_mask, uint, 0644); @@ -192,88 +193,15 @@ static inline u8 get_sta_index(struct ieee80211_vif *vif, sta_priv->sta_index; } -#define DEFINE(s) [s] = #s - -static const char * const wcn36xx_caps_names[] = { - DEFINE(MCC), - DEFINE(P2P), - DEFINE(DOT11AC), - DEFINE(SLM_SESSIONIZATION), - DEFINE(DOT11AC_OPMODE), - DEFINE(SAP32STA), - DEFINE(TDLS), - DEFINE(P2P_GO_NOA_DECOUPLE_INIT_SCAN), - DEFINE(WLANACTIVE_OFFLOAD), - DEFINE(BEACON_OFFLOAD), - DEFINE(SCAN_OFFLOAD), - DEFINE(ROAM_OFFLOAD), - DEFINE(BCN_MISS_OFFLOAD), - DEFINE(STA_POWERSAVE), - DEFINE(STA_ADVANCED_PWRSAVE), - DEFINE(AP_UAPSD), - DEFINE(AP_DFS), - DEFINE(BLOCKACK), - DEFINE(PHY_ERR), - DEFINE(BCN_FILTER), - DEFINE(RTT), - DEFINE(RATECTRL), - DEFINE(WOW), - DEFINE(WLAN_ROAM_SCAN_OFFLOAD), - DEFINE(SPECULATIVE_PS_POLL), - DEFINE(SCAN_SCH), - DEFINE(IBSS_HEARTBEAT_OFFLOAD), - DEFINE(WLAN_SCAN_OFFLOAD), - DEFINE(WLAN_PERIODIC_TX_PTRN), - DEFINE(ADVANCE_TDLS), - DEFINE(BATCH_SCAN), - DEFINE(FW_IN_TX_PATH), - DEFINE(EXTENDED_NSOFFLOAD_SLOT), - DEFINE(CH_SWITCH_V1), - DEFINE(HT40_OBSS_SCAN), - DEFINE(UPDATE_CHANNEL_LIST), - DEFINE(WLAN_MCADDR_FLT), - DEFINE(WLAN_CH144), - DEFINE(NAN), - DEFINE(TDLS_SCAN_COEXISTENCE), - DEFINE(LINK_LAYER_STATS_MEAS), - DEFINE(MU_MIMO), - DEFINE(EXTENDED_SCAN), - DEFINE(DYNAMIC_WMM_PS), - DEFINE(MAC_SPOOFED_SCAN), - DEFINE(BMU_ERROR_GENERIC_RECOVERY), - DEFINE(DISA), - DEFINE(FW_STATS), - DEFINE(WPS_PRBRSP_TMPL), - DEFINE(BCN_IE_FLT_DELTA), - DEFINE(TDLS_OFF_CHANNEL), - DEFINE(RTT3), - DEFINE(MGMT_FRAME_LOGGING), - DEFINE(ENHANCED_TXBD_COMPLETION), - DEFINE(LOGGING_ENHANCEMENT), - DEFINE(EXT_SCAN_ENHANCED), - DEFINE(MEMORY_DUMP_SUPPORTED), - DEFINE(PER_PKT_STATS_SUPPORTED), - DEFINE(EXT_LL_STAT), - DEFINE(WIFI_CONFIG), - DEFINE(ANTENNA_DIVERSITY_SELECTION), -}; - -#undef DEFINE - -static const char *wcn36xx_get_cap_name(enum place_holder_in_cap_bitmap x) -{ - if (x >= ARRAY_SIZE(wcn36xx_caps_names)) - return "UNKNOWN"; - return wcn36xx_caps_names[x]; -} - static void wcn36xx_feat_caps_info(struct wcn36xx *wcn) { int i; for (i = 0; i < MAX_FEATURE_SUPPORTED; i++) { - if (get_feat_caps(wcn->fw_feat_caps, i)) - wcn36xx_dbg(WCN36XX_DBG_MAC, "FW Cap %s\n", wcn36xx_get_cap_name(i)); + if (wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, i)) { + wcn36xx_dbg(WCN36XX_DBG_MAC, "FW Cap %s\n", + wcn36xx_firmware_get_cap_name(i)); + } } } @@ -705,7 +633,7 @@ static int wcn36xx_hw_scan(struct ieee80211_hw *hw, { struct wcn36xx *wcn = hw->priv; - if (!get_feat_caps(wcn->fw_feat_caps, SCAN_OFFLOAD)) { + if (!wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, SCAN_OFFLOAD)) { /* fallback to mac80211 software scan */ return 1; } @@ -743,7 +671,7 @@ static void wcn36xx_cancel_hw_scan(struct ieee80211_hw *hw, wcn->scan_aborted = true; mutex_unlock(&wcn->scan_lock); - if (get_feat_caps(wcn->fw_feat_caps, SCAN_OFFLOAD)) { + if (wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, SCAN_OFFLOAD)) { /* ieee80211_scan_completed will be called on FW scan * indication */ wcn36xx_smd_stop_hw_scan(wcn); diff --git a/drivers/net/wireless/ath/wcn36xx/smd.c b/drivers/net/wireless/ath/wcn36xx/smd.c index 7ac9a1e6f768..d2a994fee812 100644 --- a/drivers/net/wireless/ath/wcn36xx/smd.c +++ b/drivers/net/wireless/ath/wcn36xx/smd.c @@ -22,6 +22,7 @@ #include <linux/bitops.h> #include <linux/rpmsg.h> #include "smd.h" +#include "firmware.h" struct wcn36xx_cfg_val { u32 cfg_id; @@ -295,7 +296,7 @@ static void wcn36xx_smd_set_sta_vht_params(struct wcn36xx *wcn, sta_params->vht_capable = sta->deflink.vht_cap.vht_supported; sta_params->vht_ldpc_enabled = is_cap_supported(caps, IEEE80211_VHT_CAP_RXLDPC); - if (get_feat_caps(wcn->fw_feat_caps, MU_MIMO)) { + if (wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, MU_MIMO)) { sta_params->vht_tx_mu_beamformee_capable = is_cap_supported(caps, IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); if (sta_params->vht_tx_mu_beamformee_capable) @@ -2431,49 +2432,6 @@ out: return ret; } -void set_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap) -{ - int arr_idx, bit_idx; - - if (cap < 0 || cap > 127) { - wcn36xx_warn("error cap idx %d\n", cap); - return; - } - - arr_idx = cap / 32; - bit_idx = cap % 32; - bitmap[arr_idx] |= (1 << bit_idx); -} - -int get_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap) -{ - int arr_idx, bit_idx; - - if (cap < 0 || cap > 127) { - wcn36xx_warn("error cap idx %d\n", cap); - return -EINVAL; - } - - arr_idx = cap / 32; - bit_idx = cap % 32; - - return (bitmap[arr_idx] & (1 << bit_idx)) ? 1 : 0; -} - -void clear_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap) -{ - int arr_idx, bit_idx; - - if (cap < 0 || cap > 127) { - wcn36xx_warn("error cap idx %d\n", cap); - return; - } - - arr_idx = cap / 32; - bit_idx = cap % 32; - bitmap[arr_idx] &= ~(1 << bit_idx); -} - int wcn36xx_smd_feature_caps_exchange(struct wcn36xx *wcn) { struct wcn36xx_hal_feat_caps_msg msg_body, *rsp; @@ -2482,11 +2440,12 @@ int wcn36xx_smd_feature_caps_exchange(struct wcn36xx *wcn) mutex_lock(&wcn->hal_mutex); INIT_HAL_MSG(msg_body, WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_REQ); - set_feat_caps(msg_body.feat_caps, STA_POWERSAVE); + wcn36xx_firmware_set_feat_caps(msg_body.feat_caps, STA_POWERSAVE); if (wcn->rf_id == RF_IRIS_WCN3680) { - set_feat_caps(msg_body.feat_caps, DOT11AC); - set_feat_caps(msg_body.feat_caps, WLAN_CH144); - set_feat_caps(msg_body.feat_caps, ANTENNA_DIVERSITY_SELECTION); + wcn36xx_firmware_set_feat_caps(msg_body.feat_caps, DOT11AC); + wcn36xx_firmware_set_feat_caps(msg_body.feat_caps, WLAN_CH144); + wcn36xx_firmware_set_feat_caps(msg_body.feat_caps, + ANTENNA_DIVERSITY_SELECTION); } PREPARE_HAL_BUF(wcn->hal_buf, msg_body); @@ -3300,7 +3259,7 @@ int wcn36xx_smd_add_beacon_filter(struct wcn36xx *wcn, size_t payload_size; int ret; - if (!get_feat_caps(wcn->fw_feat_caps, BCN_FILTER)) + if (!wcn36xx_firmware_get_feat_caps(wcn->fw_feat_caps, BCN_FILTER)) return -EOPNOTSUPP; mutex_lock(&wcn->hal_mutex); diff --git a/drivers/net/wireless/ath/wcn36xx/smd.h b/drivers/net/wireless/ath/wcn36xx/smd.h index 3fd598ac2a27..cf15cde2a364 100644 --- a/drivers/net/wireless/ath/wcn36xx/smd.h +++ b/drivers/net/wireless/ath/wcn36xx/smd.h @@ -125,9 +125,6 @@ int wcn36xx_smd_keep_alive_req(struct wcn36xx *wcn, int wcn36xx_smd_dump_cmd_req(struct wcn36xx *wcn, u32 arg1, u32 arg2, u32 arg3, u32 arg4, u32 arg5); int wcn36xx_smd_feature_caps_exchange(struct wcn36xx *wcn); -void set_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap); -int get_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap); -void clear_feat_caps(u32 *bitmap, enum place_holder_in_cap_bitmap cap); int wcn36xx_smd_add_ba_session(struct wcn36xx *wcn, struct ieee80211_sta *sta, diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs.c b/drivers/phy/qualcomm/phy-qcom-usb-hs.c index 53e46c220a3a..793197512ff2 100644 --- a/drivers/phy/qualcomm/phy-qcom-usb-hs.c +++ b/drivers/phy/qualcomm/phy-qcom-usb-hs.c @@ -37,6 +37,7 @@ struct qcom_usb_hs_phy { struct ulpi_seq *init_seq; struct extcon_dev *vbus_edev; struct notifier_block vbus_notify; + u8 enable_vbus_pullup:1; }; static int qcom_usb_hs_phy_set_mode(struct phy *phy, @@ -105,6 +106,23 @@ qcom_usb_hs_phy_vbus_notifier(struct notifier_block *nb, unsigned long event, return ulpi_write(uphy->ulpi, addr, ULPI_MISC_A_VBUSVLDEXT); } +static int qcom_usb_hs_phy_enable_vbus_pullup(struct ulpi *ulpi, bool enable) +{ + u8 addr; + int ret; + + if (enable) + addr = ULPI_SET(ULPI_MISC_A); + else + addr = ULPI_CLR(ULPI_MISC_A); + + ret = ulpi_write(ulpi, addr, ULPI_MISC_A_VBUSVLDEXTSEL); + if (ret) + return ret; + + return ulpi_write(ulpi, addr, ULPI_MISC_A_VBUSVLDEXT); +} + static int qcom_usb_hs_phy_power_on(struct phy *phy) { struct qcom_usb_hs_phy *uphy = phy_get_drvdata(phy); @@ -154,6 +172,12 @@ static int qcom_usb_hs_phy_power_on(struct phy *phy) goto err_ulpi; } + if (uphy->enable_vbus_pullup) { + ret = qcom_usb_hs_phy_enable_vbus_pullup(ulpi, true); + if (ret) + goto err_ulpi; + } + if (uphy->vbus_edev) { state = extcon_get_state(uphy->vbus_edev, EXTCON_USB); /* setup initial state */ @@ -180,10 +204,19 @@ err_sleep: static int qcom_usb_hs_phy_power_off(struct phy *phy) { struct qcom_usb_hs_phy *uphy = phy_get_drvdata(phy); + struct ulpi *ulpi = uphy->ulpi; + int ret; if (uphy->vbus_edev) extcon_unregister_notifier(uphy->vbus_edev, EXTCON_USB, &uphy->vbus_notify); + + if (uphy->enable_vbus_pullup) { + ret = qcom_usb_hs_phy_enable_vbus_pullup(ulpi, false); + if (ret) + return ret; + } + regulator_disable(uphy->v3p3); regulator_disable(uphy->v1p8); clk_disable_unprepare(uphy->sleep_clk); @@ -229,6 +262,9 @@ static int qcom_usb_hs_phy_probe(struct ulpi *ulpi) /* NUL terminate */ uphy->init_seq[size / 2].addr = uphy->init_seq[size / 2].val = 0; + if (of_property_read_bool(ulpi->dev.of_node, "qcom,enable-vbus-pullup")) + uphy->enable_vbus_pullup = 1; + uphy->ref_clk = clk = devm_clk_get(&ulpi->dev, "ref"); if (IS_ERR(clk)) return PTR_ERR(clk); diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h index 99440baa6458..20af54ba1c4a 100644 --- a/drivers/usb/chipidea/ci.h +++ b/drivers/usb/chipidea/ci.h @@ -466,4 +466,7 @@ void ci_platform_configure(struct ci_hdrc *ci); void dbg_create_files(struct ci_hdrc *ci); void dbg_remove_files(struct ci_hdrc *ci); + +void ci_platform_set_pin_state(struct ci_hdrc *ci, struct pinctrl_state *pins); + #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */ diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 5359b2a2e4d2..43a391fd20af 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -183,6 +183,22 @@ u8 hw_port_test_get(struct ci_hdrc *ci) return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC); } +/** + * ci_platform_set_pin_state: set target pinctrl state with optional delay + * + * @ci: the controller + * @pins: the target pin-state + * + * This function returns nothing + */ +void ci_platform_set_pin_state(struct ci_hdrc *ci, struct pinctrl_state *pins) +{ + pinctrl_select_state(ci->platdata->pctl, pins); + if (ci->platdata->pin_switch_delay_us) + usleep_range(ci->platdata->pin_switch_delay_us, + ci->platdata->pin_switch_delay_us + 50); +} + static void hw_wait_phy_stable(void) { /* @@ -807,6 +823,9 @@ static int ci_get_platdata(struct device *dev, if (!platdata->enter_lpm) platdata->enter_lpm = ci_hdrc_enter_lpm_common; + of_property_read_u32(dev->of_node, "pin-switch-delay-us", + &platdata->pin_switch_delay_us); + return 0; } diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c index bdc3885c0d49..3b7f427266c9 100644 --- a/drivers/usb/chipidea/host.c +++ b/drivers/usb/chipidea/host.c @@ -163,8 +163,7 @@ static int host_start(struct ci_hdrc *ci) } if (ci->platdata->pins_host) - pinctrl_select_state(ci->platdata->pctl, - ci->platdata->pins_host); + ci_platform_set_pin_state(ci, ci->platdata->pins_host); ci->hcd = hcd; @@ -218,8 +217,8 @@ static void host_stop(struct ci_hdrc *ci) ci->otg.host = NULL; if (ci->platdata->pins_host && ci->platdata->pins_default) - pinctrl_select_state(ci->platdata->pctl, - ci->platdata->pins_default); + ci_platform_set_pin_state(ci, ci->platdata->pins_default); + } diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c index 3b8bf6daf7d0..b57f35b878a0 100644 --- a/drivers/usb/chipidea/udc.c +++ b/drivers/usb/chipidea/udc.c @@ -2140,8 +2140,7 @@ void ci_hdrc_gadget_destroy(struct ci_hdrc *ci) static int udc_id_switch_for_device(struct ci_hdrc *ci) { if (ci->platdata->pins_device) - pinctrl_select_state(ci->platdata->pctl, - ci->platdata->pins_device); + ci_platform_set_pin_state(ci, ci->platdata->pins_device); if (ci->is_otg) /* Clear and enable BSV irq */ @@ -2163,8 +2162,7 @@ static void udc_id_switch_for_host(struct ci_hdrc *ci) ci->vbus_active = 0; if (ci->platdata->pins_device && ci->platdata->pins_default) - pinctrl_select_state(ci->platdata->pctl, - ci->platdata->pins_default); + ci_platform_set_pin_state(ci, ci->platdata->pins_default); } /** diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index edf3342507f1..a9876761a0a3 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -94,6 +94,7 @@ struct ci_hdrc_platform_data { u16 wIndex, char *buf, u16 wLength, bool *done, unsigned long *flags); void (*enter_lpm)(struct ci_hdrc *ci, bool enable); + u32 pin_switch_delay_us; }; /* Default offset of capability registers */ |