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path: root/drivers/gpu/drm/radeon/atombios_crtc.c
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2014-02-13drm/radeon: disable ss on DP for DCE3.xAlex Deucher
commit d8e24525094200601236fa64a54cf73e3d682f2e upstream. Seems to cause problems with certain DP monitors. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=40699 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-01-09drm/radeon: add missing display tiling setup for olandAlex Deucher
commit 227ae10f17a5f2fd1307b7e582b603ef7bbb7e97 upstream. Fixes improperly set up display params for 2D tiling on oland. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-12-04drm/radeon: don't share PPLLs on DCE4.1Alex Deucher
commit 70471860ff9f335c60c004d42ebd48945bfa5403 upstream. Sharing PPLLs seems to cause problems on some boards. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=45334 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-05-20drm/radeon: Remove superfluous variableNiels Ole Salscheider
bool in_mode_set from struct radeon_crtc is not used anymore. Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-01drm/radeon: use frac fb div on RS780/RS880Alex Deucher
Monitors seem to prefer it. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=37696 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-02-05drm/radeon/dce6: fix display powergatingAlex Deucher
Only enable it when we disable the display rather than at DPMS time since enabling it requires a full modeset to restore the display state. Fixes blank screens in certain cases. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-12-07drm/radeon/dce32+: use fractional fb dividers for high clocksAlex Deucher
Fixes flickering with some high res montiors. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> CC: stable@vger.kernel.org
2012-11-27radeon: fix pll/ctrc mapping on dce2 and dce3 hardwareJerome Glisse
This fix black screen on resume issue that some people are experiencing. There is a bug in the atombios code regarding pll/crtc mapping. The atombios code reverse the logic for the pll and crtc mapping. agd5f: drop unnecessary crtc id check, cc stable in case we miss 3.7. This fixes the root cause that was worked around by commits: drm/radeon: allocate PPLLs from low to high drm/radeon/dce3: switch back to old pll allocation order for discrete Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-11-07drm/radeon/dce3: switch back to old pll allocation order for discreteAlex Deucher
The order shouldn't matter, but this seems to cause regressions for certain specific cases. This should fix it for now. We probably need to investigate a proper fix in the next development cycle. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Andy Furniss <andyqos@ukfsn.org>
2012-10-15drm/radeon: allocate PPLLs from low to highAlex Deucher
The order shouldn't matter, but there have been problems reported on certain older asics. This behaves more like the original code before the PPLL allocation rework. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Markus Trippelsdorf <markus@trippelsdorf.de>
2012-09-27drm/radeon: validate PPLL in crtc fixupAlex Deucher
This allows us to bail if we can't support the requested setup from a PPLL perspective. Prevents broken setups from being attempted. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-27drm/radeon: work around KMS modeset limitations in PLL allocation (v2)Alex Deucher
Since the current KMS API sets the mode independantly on each crtc, we may end up with resource conflicts. The PLL allocation is one of those cases. In the following example we have 3 crtcs in use driving 2 DVI connectors and 1 DP connector. On the initial kernel modeset for fbdev, the display topology ends up as follows: crtc0 -> DP-0 crtc1 -> DVI-0 crtc2 -> DVI-1 Because this is the first modeset, all of the PLLs are available as none have been assigned. So we end up with the following: crtc0 uses DCPLL crtc1 uses PPLL2 crtc2 uses PPLL1 When X starts, it assigns a different topology: crtc0 -> DVI-0 crtc1 -> DP-0 crtc2 -> DVI-1 However, since the KMS API is per crtc, we set the mode on each crtc independantly. When it comes time to set the mode on crtc0, the topology for crtc1 and crtc2 are still intact. crtc1 and crtc2 are already assigned PPLL2 and PPLL1 so when it comes time to set the mode on crtc0, crtc1 and crtc2 have not been torn down yet, so there appears to be no PLLs available. In reality, we are reconfiguring the entire display topology, however, since each crtc is handled independantly, we don't know that in the driver at each crtc mode set time. This patch checks to see if the same connector is being driven by another crtc, and if so, uses the PLL already associated with it. v2: store connector in the radeon crtc struct, simplify checking. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: make non-DP PPLL sharing more robustAlex Deucher
Compare the adjusted clock as well as the crtc mode clock. This handles cases where the driver adjusts the clock for specific special cases. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: store the encoder in the radeon_crtcAlex Deucher
This saves lots of lookups later. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: rework crtc pll setup to better support PPLL sharingAlex Deucher
We need the calculate the pixel clock before allocating a PPLL in order to insure the clocks really match. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: allow PPLL sharing on non-DP displaysAlex Deucher
If several non-DP displays use the same pixel clock we can use the same PPLL for all of them. If all relevant displays have the same pixel clock, this allows the driver to: - use fewer PPLLs which saves power - support more than two non-DP displays on DCE4+ The current drm modesetting infrastructure doesn't really provide a good framework for validating combinations that work or won't work, so it's possible you could go from a working configuration to a non-working one by changing the mode a one of the displays. However, there this is better than what was there before. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon/dce3: use a single PPLL for all DP displaysAlex Deucher
If possible, use a single PPLL for multiple DP displays on DCE3.x. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon: rework pll selection (v4)Alex Deucher
For DP we can use the same PPLL for all active DP encoders. Take advantage of that to prevent cases where we may end up sharing a PPLL between DP and non-DP which won't work. Also clean up the code a bit. v2: - fix missing pll_id assignment in crtc init v3: - fix DP PPLL check - document functions - break in main encoder search loop after matching. no need to keep checking additional encoders. v4: - same as v3, but re-apply to drm-next as the corner cases are fixed properly in subsequent patches. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=54471 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-20drm/radeon/atom: fix typo in SetPixelClock handlingAlex Deucher
MiscInfo field should be programmed with the crtc id rather than the pll id. However, at this point the two are the same for chips with this version of the table. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-17Revert "drm/radeon: rework pll selection (v3)"Alex Deucher
This reverts commit 985f61f7ee647ad570c05eab0b74915da2ac8e19. This commit fixed certain cases, but ended up regressing others due to limitations in the current KMS API. A proper fix is too invasive for 3.6. Push it back to 3.7. Reported-by: Andres Freund <andres@anarazel.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-13drm/radeon: rework pll selection (v3)Alex Deucher
For DP we can use the same PPLL for all active DP encoders. Take advantage of that to prevent cases where we may end up sharing a PPLL between DP and non-DP which won't work. Also clean up the code a bit. v2: - fix missing pll_id assignment in crtc init v3: - fix DP PPLL check - document functions - break in main encoder search loop after matching. no need to keep checking additional encoders. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=54471 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-08-29drm/radeon/atom: powergating fixes for DCE6Alex Deucher
Power gating is per crtc pair, but the powergating registers should be called individually. The hw handles power up/down properly. The pair is powered up if either crtc in the pair is powered up and the pair is not powered down until both crtcs in the pair are powered down. This simplifies programming and should save additional power as the previous code never actually power gated the crtc pair. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-08-29drm/radeon: don't disable plls that are in use by other crtcsAlex Deucher
Some plls are shared for DP. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-08-21drm/radeon/ss: use num_crtc rather than hardcoded 6Alex Deucher
When checking if a pll is in use. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-08-20drm/radeon: avoid turning off spread spectrum for used pllJerome Glisse
If spread spectrum is enabled and in use for a given pll we should not turn it off as it will lead to turning off display for crtc that use the pll (this behavior was observed on chelsea edp). Signed-off-by: Jerome Glisse <jglisse@redhat.com> Cc: stable@vger.kernel.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-13drm/radeon: fix ordering in pll picking on dce4+Alex Deucher
No functional change, but re-order the cases so they evaluate properly due to the way the DCE macros work. Noticed by kallisti5 on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-13drm/radeon: properly handle crtc powergatingAlex Deucher
Need to make sure the crtc is gated on before modesetting. Explicitly gate the crtc on in prepare() and set a flag so that the dpms functions don't gate it off during mode set. Noticed by sylware on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-07-19drm: Make the .mode_fixup() operations mode argument a const pointerLaurent Pinchart
The passed mode must not be modified by the operation, make it const. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-07-18drm/radeon: fix SS setup for DCPLLAlex Deucher
Need to actually set the SS parameters rather than just 0. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-07-18drm/radeon: fix up pll selection on DCE5/6Alex Deucher
Selecting ATOM_PPLL_INVALID should be equivalent as the DCPLL or PPLL0 are already programmed for the DISPCLK, but the preferred method is to always specify the PLL selected. SetPixelClock will check the parameters and skip the programming if the PLL is already set up. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-06-20drm/radeon: SI tiling fixes for displayAlex Deucher
- Use the correct union for getting the tiling info - Properly init the PIPE_CONFIG field for SI Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-05-07Merge tag 'v3.4-rc6' into drm-intel-nextDaniel Vetter
Conflicts: drivers/gpu/drm/i915/intel_display.c Ok, this is a fun story of git totally messing things up. There /shouldn't/ be any conflict in here, because the fixes in -rc6 do only touch functions that have not been changed in -next. The offending commits in drm-next are 14415745b2..1fa611065 which simply move a few functions from intel_display.c to intel_pm.c. The problem seems to be that git diff gets completely confused: $ git diff 14415745b2..1fa611065 is a nice mess in intel_display.c, and the diff leaks into totally unrelated functions, whereas $git diff --minimal 14415745b2..1fa611065 is exactly what we want. Unfortunately there seems to be no way to teach similar smarts to the merge diff and conflict generation code, because with the minimal diff there really shouldn't be any conflicts. For added hilarity, every time something in that area changes the + and - lines in the diff move around like crazy, again resulting in new conflicts. So I fear this mess will stay with us for a little longer (and might result in another backmerge down the road). Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-04-28drm/radeon/kms: need to set up ss on DP bridges as wellAlex Deucher
Makes Nutmeg DP to VGA bridges work for me. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=42490 Noticed by Jerome Glisse (after weeks of debugging). Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-04-27drm/radeon/kms: use frac fb div on APUsAlex Deucher
Seems to be more stable on certain monitors. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48880 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-04-24drm/radeon/kms: improve bpc handling (v2)Alex Deucher
Improve handling of bpc (bits per color) in radeon. In most cases we want 8 except for HDMI, DP, LVDS, and eDP. v2: handle DP better. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-26drm/radeon/kms/atom: force bpc to 8 for nowAlex Deucher
Using the bpc (bits per color) specified by the monitor can cause problems in some cases. Until we get a better handle on how to deal with those cases, just use a bpc of 8. Reported-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms/DCE6.1: ss is not supported on the internal ppllsAlex Deucher
It's handled via external clock. It should already be protected by the external ss flag, but add an explicit check just in case. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms: disable PPLL0 on DCE6.1 when not in useAlex Deucher
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms: Adjust pll picker for DCE6.1Alex Deucher
On TN, UNIPHYA always uses PPLL2, UNIPHYB/C/D/E/F can use either PPLL1 or PPLL0. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms: DCE6.1 disp eng pll updatesAlex Deucher
DCE6.1 uses EXT_PLL1 for disp eng. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms: DCE6 disp eng pll updatesAlex Deucher
Rename the function to better match the functionality. DCPLL became PLL0 on DCE6. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms/atom: add support for crtc power gatingAlex Deucher
Each pair of crtcs (0/1, 2/3, 4/5) can be power gated. Make sure the power is applied when the crtc is in use and only power down the pair when both are off. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms/atom: DCE6 no longer has crtcmemreq bitsAlex Deucher
The hw no longer has the bits and the table is removed. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-02-13drm/radeon: add support for evergreen/ni tiling informations v11Jerome Glisse
evergreen and northern island gpu needs more informations for 2D tiling than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace to provide those. The v8 cs checking change to track color view on r6xx/r7xx doesn't affect old userspace as old userspace always emited 0 for this register. v2 fix r6xx/r7xx 2D tiling computation v3 fix r6xx/r7xx height align for untiled surface & add support for tile split on evergreen and newer v4 improve tiling debugging output v5 fix tile split code for evergreen and newer v6 set proper tile split for crtc register v7 fix tile split limit value v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs checking, update safe reg for r600, evergreen and cayman. Evergreen checking need some work around for stencil alignment issues v9 fix tile split value range, fix compressed texture handling and mipmap calculation, allow evergreen check to be silencious in front of current broken userspace (depth/stencil alignment issue) v10 fix eg 3d texture and compressed texture, fix r600 depth array, fix r600 color view computation, add support for evergreen stencil split v11 more verbose debugging in some case Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-02-01drm/radeon: Set DESKTOP_HEIGHT register to the framebuffer (not mode) height.Michel Dänzer
The value of this register is transferred to the V_COUNTER register at the beginning of vertical blank. V_COUNTER is the reference for VLINE waits and goes from VIEWPORT_Y_START to VIEWPORT_Y_START+VIEWPORT_HEIGHT during scanout, so if VIEWPORT_Y_START is not 0, V_COUNTER actually went backwards at the beginning of vertical blank, and VLINE waits excluding the whole scanout area could never finish (possibly only if VIEWPORT_Y_START is larger than the length of vertical blank in scanlines). Setting DESKTOP_HEIGHT to the framebuffer height should prevent this for any kind of VLINE wait. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=45329 . CC: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-24drm/radeon/kms: refine TMDS dual link checksAlex Deucher
HDMI 1.3 defines single link clocks up to 340 Mhz. Refine the current dual link checks to only enable dual link for DVI > 165 Mhz or HDMI > 340 Mhz if the hw supports HDMI 1.3 (DCE3+). Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=44755 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-24drm/radeon/kms: move disp eng pll setup to init pathAlex Deucher
We really only need to set it up once on init or resume rather than on every mode set. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-20drm/radeon/kms: don't use 0 bpc for adjusting hdmi clockDave Airlie
If the bpc is set from the connector is 0, we then use it later to adjust in a special case the HDMI pixel clock, however if the bpc is 0, we end up passing a 0 pixel clock into the code. I'm not sure if this is the correct answer or if we should avoid the HDMI clock adjustment for 0 values. This fixes a divide by 0 on my Llano system with a HDMI monitor and hdmi audio enabled. Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-20Merge tag 'v3.2-rc6' of /home/airlied/devel/kernel/linux-2.6 into drm-core-nextDave Airlie
Merge in the upstream tree to bring in the mainline fixes. Conflicts: drivers/gpu/drm/exynos/exynos_drm_fbdev.c drivers/gpu/drm/nouveau/nouveau_sgdma.c
2011-12-20drm: Replace pitch with pitches[] in drm_framebufferVille Syrjälä
Otherwise each driver would need to keep the information inside their own framebuffer object structure. Also add offsets[]. BOs on the other hand are driver specific, so those can be kept in driver specific structures. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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