diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2013-04-09 15:54:16 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2013-04-09 16:01:52 +0200 |
| commit | 9bc128e16bb82c046d6972171de572affc5c4cbf (patch) | |
| tree | 7c6dbe7f69771e9563d39f3be8a4854bed30d861 | |
| parent | 835f9c38bbb4498c3d43b7466964bdadbb1fd244 (diff) | |
| parent | f6f1bdac9d3006e246e82672322dcd7e7e0863fd (diff) | |
Merge tag 'ux500-multiplatform-asoc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/multiplatform
From Linus Walleij <linus.walleij@linaro.org>:
Ux500 multiplatform support. This tag builds upon the MFD-specific base
tag "ux500-multiplatform-mfd". This removes all <mach/*> dependencies
and makes the ux500 fully multi-platform.
* tag 'ux500-multiplatform-asoc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: build hotplug.o for ARMv7-a
ARM: ux500: move to multiplatform
ARM: ux500: make remaining headers local
ARM: ux500: make irqs.h local to platform
ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>
staging: ste_rmi4: kill platform_data hack
ARM: ux500: move mach/msp.h to <linux/platform_data/*>
clk: ux500: pass clock base adresses in init call
ARM: ux500: make debug macro stand-alone
ARM: ux500: move debugmacro to debug includes
ARM: ux500: split out prcmu initialization
mfd: db8500-prcmu: drop unused includes
ARM: ux500: move PM-related PRCMU functions to machine
mfd: db8500-prcmu: get base address from resource
mfd: prcmu: pass a base and size with the early initcall
Conflicts:
arch/arm/Kconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
57 files changed, 699 insertions, 766 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0036238d4b7..8bca2f382e0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -853,22 +853,6 @@ config ARCH_U300 help Support for ST-Ericsson U300 series mobile platforms. -config ARCH_U8500 - bool "ST-Ericsson U8500 Series" - depends on MMU - select ARCH_HAS_CPUFREQ - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select CLKDEV_LOOKUP - select CPU_V7 - select GENERIC_CLOCKEVENTS - select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 - select SPARSE_IRQ - help - Support for ST-Ericsson's Ux500 architecture - - config ARCH_DAVINCI bool "TI DaVinci" select ARCH_HAS_HOLES_MEMORYMODEL diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 5310ce2bc92..719ef2855b8 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -432,6 +432,13 @@ choice Say Y here if you want the debug print routines to direct their output to the uart1 port on SiRFmarco devices. + config DEBUG_UX500_UART + depends on ARCH_U8500 + bool "Use Ux500 UART for low-level debug" + help + Say Y here if you want kernel low-level debugging support + on Ux500 based platforms. + config DEBUG_VEXPRESS_UART0_DETECT bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" depends on ARCH_VEXPRESS && CPU_CP15_MMU @@ -620,6 +627,7 @@ config DEBUG_LL_INCLUDE DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/tegra.S" if DEBUG_TEGRA_UART + default "debug/ux500.S" if DEBUG_UX500_UART default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 default "mach/debug-macro.S" diff --git a/arch/arm/include/debug/ux500.S b/arch/arm/include/debug/ux500.S new file mode 100644 index 00000000000..2848857f5b6 --- /dev/null +++ b/arch/arm/include/debug/ux500.S @@ -0,0 +1,48 @@ +/* + * Debugging macro include header + * + * Copyright (C) 2009 ST-Ericsson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + + +#if CONFIG_UX500_DEBUG_UART > 2 +#error Invalid Ux500 debug UART +#endif + +/* + * DEBUG_LL only works if only one SOC is built in. We don't use #else below + * in order to get "__UX500_UART redefined" warnings if more than one SOC is + * built, so that there's some hint during the build that something is wrong. + */ + +#ifdef CONFIG_UX500_SOC_DB8500 +#define U8500_UART0_PHYS_BASE (0x80120000) +#define U8500_UART1_PHYS_BASE (0x80121000) +#define U8500_UART2_PHYS_BASE (0x80007000) +#define U8500_UART0_VIRT_BASE (0xa8120000) +#define U8500_UART1_VIRT_BASE (0xa8121000) +#define U8500_UART2_VIRT_BASE (0xa8007000) +#define __UX500_PHYS_UART(n) U8500_UART##n##_PHYS_BASE +#define __UX500_VIRT_UART(n) U8500_UART##n##_VIRT_BASE +#endif + +#if !defined(__UX500_PHYS_UART) || !defined(__UX500_VIRT_UART) +#error Unknown SOC +#endif + +#define UX500_PHYS_UART(n) __UX500_PHYS_UART(n) +#define UX500_VIRT_UART(n) __UX500_VIRT_UART(n) +#define UART_PHYS_BASE UX500_PHYS_UART(CONFIG_UX500_DEBUG_UART) +#define UART_VIRT_BASE UX500_VIRT_UART(CONFIG_UX500_DEBUG_UART) + + .macro addruart, rp, rv, tmp + ldr \rp, =UART_PHYS_BASE @ no, physical address + ldr \rv, =UART_VIRT_BASE @ yes, virtual address + .endm + +#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 3e5bbd0e5b2..eeea3bf4dff 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -1,3 +1,17 @@ +config ARCH_U8500 + bool "ST-Ericsson U8500 Series" if ARCH_MULTI_V7 + depends on MMU + select ARCH_HAS_CPUFREQ + select ARCH_REQUIRE_GPIOLIB + select ARM_AMBA + select CLKDEV_LOOKUP + select CPU_V7 + select GENERIC_CLOCKEVENTS + select HAVE_SMP + select MIGHT_HAVE_CACHE_L2X0 + help + Support for ST-Ericsson's Ux500 architecture + if ARCH_U8500 config UX500_SOC_COMMON diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile index f24710dfc39..bf9b6be5b18 100644 --- a/arch/arm/mach-ux500/Makefile +++ b/arch/arm/mach-ux500/Makefile @@ -3,7 +3,7 @@ # obj-y := cpu.o devices.o devices-common.o \ - id.o usb.o timer.o + id.o usb.o timer.o pm.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o @@ -15,3 +15,5 @@ obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ board-mop500-audio.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o + +CFLAGS_hotplug.o += -march=armv7-a diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c index 7209db7cdc7..aba9e569295 100644 --- a/arch/arm/mach-ux500/board-mop500-audio.c +++ b/arch/arm/mach-ux500/board-mop500-audio.c @@ -10,10 +10,9 @@ #include <linux/platform_data/pinctrl-nomadik.h> #include <linux/platform_data/dma-ste-dma40.h> -#include <mach/devices.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/msp.h> +#include "devices.h" +#include "irqs.h" +#include <linux/platform_data/asoc-ux500-msp.h> #include "ste-dma40-db8500.h" #include "board-mop500.h" diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 0a3f30df1eb..f3976f9c404 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -13,8 +13,6 @@ #include <asm/mach-types.h> -#include <mach/hardware.h> - #include "pins-db8500.h" #include "board-mop500.h" diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 051b62c2710..f76be4ade7c 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c @@ -14,9 +14,9 @@ #include <linux/platform_data/dma-ste-dma40.h> #include <asm/mach-types.h> -#include <mach/devices.h> -#include <mach/hardware.h> +#include "devices.h" +#include "db8500-regs.h" #include "devices-db8500.h" #include "board-mop500.h" #include "ste-dma40-db8500.h" diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c index ead91c968ff..d397c19570a 100644 --- a/arch/arm/mach-ux500/board-mop500-u8500uib.c +++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c @@ -12,12 +12,15 @@ #include <linux/mfd/tc3589x.h> #include <linux/input/matrix_keypad.h> -#include <mach/irqs.h> +#include "irqs.h" #include "board-mop500.h" -/* Dummy data that can be overridden by staging driver */ -struct i2c_board_info __initdata __weak mop500_i2c3_devices_u8500[] = { +static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = { + { + I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B), + .irq = NOMADIK_GPIO_TO_IRQ(84), + }, }; /* diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c index 7037d3687e9..bdaa422da02 100644 --- a/arch/arm/mach-ux500/board-mop500-uib.c +++ b/arch/arm/mach-ux500/board-mop500-uib.c @@ -11,7 +11,6 @@ #include <linux/init.h> #include <linux/i2c.h> -#include <mach/hardware.h> #include "board-mop500.h" #include "id.h" diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index b03457881c4..0d59e1ad810 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -41,13 +41,13 @@ #include <asm/mach-types.h> #include <asm/mach/arch.h> -#include <mach/hardware.h> -#include <mach/setup.h> -#include <mach/devices.h> -#include <mach/irqs.h> +#include "setup.h" +#include "devices.h" +#include "irqs.h" #include <linux/platform_data/crypto-ux500.h> #include "ste-dma40-db8500.h" +#include "db8500-regs.h" #include "devices-db8500.h" #include "board-mop500.h" #include "board-mop500-regulators.h" @@ -206,63 +206,6 @@ struct ab8500_platform_data ab8500_platdata = { .codec = &ab8500_codec_pdata, }; -/* - * Thermal Sensor - */ - -static struct resource db8500_thsens_resources[] = { - { - .name = "IRQ_HOTMON_LOW", - .start = IRQ_PRCMU_HOTMON_LOW, - .end = IRQ_PRCMU_HOTMON_LOW, - .flags = IORESOURCE_IRQ, - }, - { - .name = "IRQ_HOTMON_HIGH", - .start = IRQ_PRCMU_HOTMON_HIGH, - .end = IRQ_PRCMU_HOTMON_HIGH, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct db8500_thsens_platform_data db8500_thsens_data = { - .trip_points[0] = { - .temp = 70000, - .type = THERMAL_TRIP_ACTIVE, - .cdev_name = { - [0] = "thermal-cpufreq-0", - }, - }, - .trip_points[1] = { - .temp = 75000, - .type = THERMAL_TRIP_ACTIVE, - .cdev_name = { - [0] = "thermal-cpufreq-0", - }, - }, - .trip_points[2] = { - .temp = 80000, - .type = THERMAL_TRIP_ACTIVE, - .cdev_name = { - [0] = "thermal-cpufreq-0", - }, - }, - .trip_points[3] = { - .temp = 85000, - .type = THERMAL_TRIP_CRITICAL, - }, - .num_trips = 4, -}; - -static struct platform_device u8500_thsens_device = { - .name = "db8500-thermal", - .resource = db8500_thsens_resources, - .num_resources = ARRAY_SIZE(db8500_thsens_resources), - .dev = { - .platform_data = &db8500_thsens_data, - }, -}; - static struct platform_device u8500_cpufreq_cooling_device = { .name = "db8500-cpufreq-cooling", }; @@ -622,7 +565,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = { &snowball_key_dev, &snowball_sbnet_dev, &snowball_gpio_en_3v3_regulator_dev, - &u8500_thsens_device, &u8500_cpufreq_cooling_device, }; diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index eaa605f5d90..16bf1ac020a 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h @@ -8,8 +8,8 @@ #define __BOARD_MOP500_H /* For NOMADIK_NR_GPIO */ -#include <mach/irqs.h> -#include <mach/msp.h> +#include "irqs.h" +#include <linux/platform_data/asoc-ux500-msp.h> #include <linux/amba/mmci.h> /* Snowball specific GPIO assignments, this board has no GPIO expander */ diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 1c1609da76c..e12cc92dfca 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c @@ -9,8 +9,8 @@ #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> -#include <mach/hardware.h> +#include "db8500-regs.h" #include "id.h" static void __iomem *l2x0_base; diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 19235cf7bbe..7a66a810274 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c @@ -28,15 +28,13 @@ #include <asm/mach/map.h> #include <asm/mach/arch.h> -#include <mach/hardware.h> -#include <mach/setup.h> -#include <mach/devices.h> -#include <mach/db8500-regs.h> -#include <mach/irqs.h> +#include "setup.h" +#include "devices.h" +#include "irqs.h" #include "devices-db8500.h" #include "ste-dma40-db8500.h" - +#include "db8500-regs.h" #include "board-mop500.h" #include "id.h" @@ -94,8 +92,6 @@ void __init u8500_map_io(void) iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc)); else iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); - - _PRCMU_BASE = __io_address(U8500_PRCMU_BASE); } static struct resource db8500_pmu_resources[] = { diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 537870d3fea..915e2636cba 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c @@ -8,7 +8,7 @@ #include <linux/platform_device.h> #include <linux/io.h> -#include <linux/mfd/db8500-prcmu.h> +#include <linux/mfd/dbx500-prcmu.h> #include <linux/clksrc-dbx500-prcmu.h> #include <linux/sys_soc.h> #include <linux/err.h> @@ -20,18 +20,17 @@ #include <linux/irqchip.h> #include <linux/irqchip/arm-gic.h> #include <linux/platform_data/clk-ux500.h> +#include <linux/platform_data/arm-ux500-pm.h> #include <asm/mach/map.h> -#include <mach/hardware.h> -#include <mach/setup.h> -#include <mach/devices.h> +#include "setup.h" +#include "devices.h" #include "board-mop500.h" +#include "db8500-regs.h" #include "id.h" -void __iomem *_PRCMU_BASE; - /* * FIXME: Should we set up the GPIO domain here? * @@ -68,13 +67,23 @@ void __init ux500_init_irq(void) * Init clocks here so that they are available for system timer * initialization. */ - if (cpu_is_u8500_family() || cpu_is_u9540()) - db8500_prcmu_early_init(); - - if (cpu_is_u8500_family() || cpu_is_u9540()) - u8500_clk_init(); - else if (cpu_is_u8540()) + if (cpu_is_u8500_family()) { + prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); + ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); + u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, + U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, + U8500_CLKRST6_BASE); + } else if (cpu_is_u9540()) { + prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1); + ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1); + u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE, + U8500_CLKRST3_BASE, U8500_CLKRST5_BASE, + U8500_CLKRST6_BASE); + } else if (cpu_is_u8540()) { + prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); + ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1); u8540_clk_init(); + } } void __init ux500_init_late(void) diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c index ce9149302cc..654115afb36 100644 --- a/arch/arm/mach-ux500/cpuidle.c +++ b/arch/arm/mach-ux500/cpuidle.c @@ -16,10 +16,13 @@ #include <linux/atomic.h> #include <linux/smp.h> #include <linux/mfd/dbx500-prcmu.h> +#include <linux/platform_data/arm-ux500-pm.h> #include <asm/cpuidle.h> #include <asm/proc-fns.h> +#include "db8500-regs.h" + static atomic_t master = ATOMIC_INIT(0); static DEFINE_SPINLOCK(master_lock); static DEFINE_PER_CPU(struct cpuidle_device, ux500_cpuidle_device); @@ -130,7 +133,7 @@ int __init ux500_idle_init(void) int ret, cpu; struct cpuidle_device *device; - /* Configure wake up reasons */ + /* Configure wake up reasons */ prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) | PRCMU_WAKEUP(ABB)); diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/db8500-regs.h index 1530d493879..b2d7a0b9862 100644 --- a/arch/arm/mach-ux500/include/mach/db8500-regs.h +++ b/arch/arm/mach-ux500/db8500-regs.h @@ -170,4 +170,32 @@ /* SoC identification number information */ #define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0) +/* Offsets to specific addresses in some IP blocks for DMA */ +#define MSP_TX_RX_REG_OFFSET 0 +#define CRYP1_RX_REG_OFFSET 0x10 +#define CRYP1_TX_REG_OFFSET 0x8 +#define HASH1_TX_REG_OFFSET 0x4 + +/* + * Macros to get at IO space when running virtually + * We dont map all the peripherals, let ioremap do + * this for us. We map only very basic peripherals here. + */ +#define U8500_IO_VIRTUAL 0xf0000000 +#define U8500_IO_PHYSICAL 0xa0000000 +/* This is where we map in the ROM to check ASIC IDs */ +#define UX500_VIRT_ROM 0xf0000000 + +/* This macro is used in assembly, so no cast */ +#define IO_ADDRESS(x) \ + (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) + +/* typesafe io address */ +#define __io_address(n) IOMEM(IO_ADDRESS(n)) + +/* Used by some plat-nomadik code */ +#define io_p2v(n) __io_address(n) + +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) + #endif diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c index 16b5f71e697..f71b3d7bd4f 100644 --- a/arch/arm/mach-ux500/devices-common.c +++ b/arch/arm/mach-ux500/devices-common.c @@ -13,8 +13,7 @@ #include <linux/platform_device.h> #include <linux/platform_data/pinctrl-nomadik.h> -#include <mach/hardware.h> -#include <mach/irqs.h> +#include "irqs.h" #include "devices-common.h" diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index f3d9419f75d..1cf94ce0fee 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -15,10 +15,10 @@ #include <linux/platform_data/dma-ste-dma40.h> #include <linux/mfd/dbx500-prcmu.h> -#include <mach/hardware.h> -#include <mach/setup.h> -#include <mach/irqs.h> +#include "setup.h" +#include "irqs.h" +#include "db8500-regs.h" #include "devices-db8500.h" #include "ste-dma40-db8500.h" @@ -199,6 +199,8 @@ struct platform_device u8500_ske_keypad_device = { struct prcmu_pdata db8500_prcmu_pdata = { .ab_platdata = &ab8500_platdata, + .ab_irq = IRQ_DB8500_AB8500, + .irq_base = IRQ_PRCMU_BASE, .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, }; diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h index dbcb35c48f0..321998320f9 100644 --- a/arch/arm/mach-ux500/devices-db8500.h +++ b/arch/arm/mach-ux500/devices-db8500.h @@ -9,7 +9,8 @@ #define __DEVICES_DB8500_H #include <linux/platform_data/usb-musb-ux500.h> -#include <mach/irqs.h> +#include "irqs.h" +#include "db8500-regs.h" #include "devices-common.h" struct ske_keypad_platform_data; diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c index ea0a2f92ca7..0f9e52b9593 100644 --- a/arch/arm/mach-ux500/devices.c +++ b/arch/arm/mach-ux500/devices.c @@ -11,8 +11,9 @@ #include <linux/io.h> #include <linux/amba/bus.h> -#include <mach/hardware.h> -#include <mach/setup.h> +#include "setup.h" + +#include "db8500-regs.h" void __init amba_add_devices(struct amba_device *devs[], int num) { diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/devices.h index cbc6f1e4104..cbc6f1e4104 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/devices.h diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c index 2f6af259015..87abcf27843 100644 --- a/arch/arm/mach-ux500/hotplug.c +++ b/arch/arm/mach-ux500/hotplug.c @@ -15,7 +15,7 @@ #include <asm/cacheflush.h> #include <asm/smp_plat.h> -#include <mach/setup.h> +#include "setup.h" /* * platform-specific code to shutdown a CPU diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c index 9f951842e1e..0d33d1a0695 100644 --- a/arch/arm/mach-ux500/id.c +++ b/arch/arm/mach-ux500/id.c @@ -14,9 +14,9 @@ #include <asm/cacheflush.h> #include <asm/mach/map.h> -#include <mach/hardware.h> -#include <mach/setup.h> +#include "setup.h" +#include "db8500-regs.h" #include "id.h" struct dbx500_asic_id dbx500_id; diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S deleted file mode 100644 index 67035223334..00000000000 --- a/arch/arm/mach-ux500/include/mach/debug-macro.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Debugging macro include header - * - * Copyright (C) 2009 ST-Ericsson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ -#include <mach/hardware.h> - -#if CONFIG_UX500_DEBUG_UART > 2 -#error Invalid Ux500 debug UART -#endif - -/* - * DEBUG_LL only works if only one SOC is built in. We don't use #else below - * in order to get "__UX500_UART redefined" warnings if more than one SOC is - * built, so that there's some hint during the build that something is wrong. - */ - -#ifdef CONFIG_UX500_SOC_DB8500 -#define __UX500_UART(n) U8500_UART##n##_BASE -#endif - -#ifndef __UX500_UART -#error Unknown SOC -#endif - -#define UX500_UART(n) __UX500_UART(n) -#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) - - .macro addruart, rp, rv, tmp - ldr \rp, =UART_BASE @ no, physical address - ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address - .endm - -#include <asm/hardware/debug-pl01x.S> diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h deleted file mode 100644 index 5201ddace50..00000000000 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson. - * - * U8500 hardware definitions - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -/* - * Macros to get at IO space when running virtually - * We dont map all the peripherals, let ioremap do - * this for us. We map only very basic peripherals here. - */ -#define U8500_IO_VIRTUAL 0xf0000000 -#define U8500_IO_PHYSICAL 0xa0000000 -/* This is where we map in the ROM to check ASIC IDs */ -#define UX500_VIRT_ROM 0xf0000000 - -/* This macro is used in assembly, so no cast */ -#define IO_ADDRESS(x) \ - (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL) - -/* typesafe io address */ -#define __io_address(n) IOMEM(IO_ADDRESS(n)) - -/* Used by some plat-nomadik code */ -#define io_p2v(n) __io_address(n) - -#include <mach/db8500-regs.h> - -#define MSP_TX_RX_REG_OFFSET 0 -#define CRYP1_RX_REG_OFFSET 0x10 -#define CRYP1_TX_REG_OFFSET 0x8 -#define HASH1_TX_REG_OFFSET 0x4 - -#ifndef __ASSEMBLY__ - -extern void __iomem *_PRCMU_BASE; - -#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) - -#endif /* __ASSEMBLY__ */ -#endif /* __MACH_HARDWARE_H */ diff --git a/arch/arm/mach-ux500/include/mach/timex.h b/arch/arm/mach-ux500/include/mach/timex.h deleted file mode 100644 index d0942c17401..00000000000 --- a/arch/arm/mach-ux500/include/mach/timex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ASM_ARCH_TIMEX_H -#define __ASM_ARCH_TIMEX_H - -#define CLOCK_TICK_RATE 110000000 - -#endif diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h deleted file mode 100644 index 36969d52e53..00000000000 --- a/arch/arm/mach-ux500/include/mach/uncompress.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __ASM_ARCH_UNCOMPRESS_H -#define __ASM_ARCH_UNCOMPRESS_H - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <linux/io.h> -#include <linux/amba/serial.h> -#include <mach/hardware.h> - -void __iomem *ux500_uart_base; - -static void putc(const char c) -{ - /* Do nothing if the UART is not enabled. */ - if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) - return; - - if (c == '\n') - putc('\r'); - - while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5)) - barrier(); - __raw_writeb(c, ux500_uart_base + UART01x_DR); -} - -static void flush(void) -{ - if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1)) - return; - while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3)) - barrier(); -} - -static inline void arch_decomp_setup(void) -{ - /* Use machine_is_foo() macro if you need to switch base someday */ - ux500_uart_base = (void __iomem *)U8500_UART2_BASE; -} - -#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/irqs-board-mop500.h index d526dd8e87d..d526dd8e87d 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h +++ b/arch/arm/mach-ux500/irqs-board-mop500.h diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/irqs-db8500.h index 68bc1497460..f3a9d5947ef 100644 --- a/arch/arm/mach-ux500/include/mach/irqs-db8500.h +++ b/arch/arm/mach-ux500/irqs-db8500.h @@ -109,31 +109,6 @@ /* Virtual interrupts corresponding to the PRCMU wakeups. */ #define IRQ_PRCMU_BASE IRQ_SOC_START -#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE) - -#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE) -#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1) -#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2) -#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3) -#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4) -#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5) -#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6) -#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7) -#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8) -#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9) -#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10) -#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11) -#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12) -#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13) -#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14) -#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15) -#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16) -#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17) -#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18) -#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19) -#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20) -#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21) -#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22) #define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23) /* diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/irqs.h index fc77b4274c8..15b2af698ed 100644 --- a/arch/arm/mach-ux500/include/mach/irqs.h +++ b/arch/arm/mach-ux500/irqs.h @@ -10,8 +10,6 @@ #ifndef ASM_ARCH_IRQS_H #define ASM_ARCH_IRQS_H -#include <mach/hardware.h> - #define IRQ_LOCALTIMER 29 #define IRQ_LOCALWDOG 30 @@ -36,14 +34,14 @@ /* This will be overridden by SoC-specific irq headers */ #define IRQ_SOC_END IRQ_SOC_START -#include <mach/irqs-db8500.h> +#include "irqs-db8500.h" #define IRQ_BOARD_START IRQ_SOC_END /* This will be overridden by board-specific irq headers */ #define IRQ_BOARD_END IRQ_BOARD_START #ifdef CONFIG_MACH_MOP500 -#include <mach/irqs-board-mop500.h> +#include "irqs-board-mop500.h" #endif #define UX500_NR_IRQS IRQ_BOARD_END diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 18f7af339dc..12ad8ad850a 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -22,9 +22,9 @@ #include <asm/smp_plat.h> #include <asm/smp_scu.h> -#include <mach/hardware.h> -#include <mach/setup.h> +#include "setup.h" +#include "db8500-regs.h" #include "id.h" /* This is called from headsmp.S to wakeup the secondary core */ diff --git a/arch/arm/mach-ux500/pm.c b/arch/arm/mach-ux500/pm.c new file mode 100644 index 00000000000..1a468f0fd22 --- /dev/null +++ b/arch/arm/mach-ux500/pm.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) ST-Ericsson SA 2010-2013 + * Author: Rickard Andersson <rickard.andersson@stericsson.com> for + * ST-Ericsson. + * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro. + * License terms: GNU General Public License (GPL) version 2 + * + */ + +#include <linux/kernel.h> +#include <linux/irqchip/arm-gic.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/platform_data/arm-ux500-pm.h> + +#include "db8500-regs.h" + +/* ARM WFI Standby signal register */ +#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130) +#define PRCM_ARM_WFI_STANDBY_WFI0 0x08 +#define PRCM_ARM_WFI_STANDBY_WFI1 0x10 +#define PRCM_IOCR (prcmu_base + 0x310) +#define PRCM_IOCR_IOFORCE 0x1 + +/* Dual A9 core interrupt management unit registers */ +#define PRCM_A9_MASK_REQ (prcmu_base + 0x328) +#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1 + +#define PRCM_A9_MASK_ACK (prcmu_base + 0x32c) +#define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c) +#define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120) +#define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124) +#define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128) +#define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C) +#define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260) +#define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264) +#define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268) +#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) + +static void __iomem *prcmu_base; + +/* This function decouple the gic from the prcmu */ +int prcmu_gic_decouple(void) +{ + u32 val = readl(PRCM_A9_MASK_REQ); + + /* Set bit 0 register value to 1 */ + writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, + PRCM_A9_MASK_REQ); + + /* Make sure the register is updated */ + readl(PRCM_A9_MASK_REQ); + + /* Wait a few cycles for the gic mask completion */ + udelay(1); + + return 0; +} + +/* This function recouple the gic with the prcmu */ +int prcmu_gic_recouple(void) +{ + u32 val = readl(PRCM_A9_MASK_REQ); + + /* Set bit 0 register value to 0 */ + writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); + + return 0; +} + +#define PRCMU_GIC_NUMBER_REGS 5 + +/* + * This function checks if there are pending irq on the gic. It only + * makes sense if the gic has been decoupled before with the + * db8500_prcmu_gic_decouple function. Disabling an interrupt only + * disables the forwarding of the interrupt to any CPU interface. It + * does not prevent the interrupt from changing state, for example + * becoming pending, or active and pending if it is already + * active. Hence, we have to check the interrupt is pending *and* is + * active. + */ +bool prcmu_gic_pending_irq(void) +{ + u32 pr; /* Pending register */ + u32 er; /* Enable register */ + void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); + int i; + + /* 5 registers. STI & PPI not skipped */ + for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { + + pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); + er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); + + if (pr & er) + return true; /* There is a pending interrupt */ + } + + return false; +} + +/* + * This function checks if there are pending interrupt on the + * prcmu which has been delegated to monitor the irqs with the + * db8500_prcmu_copy_gic_settings function. + */ +bool prcmu_pending_irq(void) +{ + u32 it, im; + int i; + + for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { + it = readl(PRCM_ARMITVAL31TO0 + i * 4); + im = readl(PRCM_ARMITMSK31TO0 + i * 4); + if (it & im) + return true; /* There is a pending interrupt */ + } + + return false; +} + +/* + * This function checks if the specified cpu is in in WFI. It's usage + * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple + * function. Of course passing smp_processor_id() to this function will + * always return false... + */ +bool prcmu_is_cpu_in_wfi(int cpu) +{ + return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : + PRCM_ARM_WFI_STANDBY_WFI0; +} + +/* + * This function copies the gic SPI settings to the prcmu in order to + * monitor them and abort/finish the retention/off sequence or state. + */ +int prcmu_copy_gic_settings(void) +{ + u32 er; /* Enable register */ + void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); + int i; + + /* We skip the STI and PPI */ + for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { + er = readl_relaxed(dist_base + + GIC_DIST_ENABLE_SET + (i + 1) * 4); + writel(er, PRCM_ARMITMSK31TO0 + i * 4); + } + + return 0; +} + +void __init ux500_pm_init(u32 phy_base, u32 size) +{ + prcmu_base = ioremap(phy_base, size); + if (!prcmu_base) { + pr_err("could not remap PRCMU for PM functions\n"); + return; + } + /* + * On watchdog reboot the GIC is in some cases decoupled. + * This will make sure that the GIC is correctly configured. + */ + prcmu_gic_recouple(); +} diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/setup.h index bddce2b4937..bddce2b4937 100644 --- a/arch/arm/mach-ux500/include/mach/setup.h +++ b/arch/arm/mach-ux500/setup.h diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index d07bbe7f04a..b6bd0efcbe6 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c @@ -14,10 +14,10 @@ #include <asm/smp_twd.h> -#include <mach/setup.h> -#include <mach/hardware.h> -#include <mach/irqs.h> +#include "setup.h" +#include "irqs.h" +#include "db8500-regs.h" #include "id.h" #ifdef CONFIG_HAVE_ARM_TWD diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c index 78ac65f62e8..2dfc72f7cd8 100644 --- a/arch/arm/mach-ux500/usb.c +++ b/arch/arm/mach-ux500/usb.c @@ -10,7 +10,7 @@ #include <linux/platform_data/usb-musb-ux500.h> #include <linux/platform_data/dma-ste-dma40.h> -#include <mach/hardware.h> +#include "db8500-regs.h" #define MUSB_DMA40_RX_CH { \ .mode = STEDMA40_MODE_LOGICAL, \ diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c index 7eee7f76835..bd4769a8448 100644 --- a/drivers/clk/ux500/clk-prcc.c +++ b/drivers/clk/ux500/clk-prcc.c @@ -13,7 +13,6 @@ #include <linux/io.h> #include <linux/err.h> #include <linux/types.h> -#include <mach/hardware.h> #include "clk.h" diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 6b889a0e90b..0c9b83d98f1 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -12,10 +12,10 @@ #include <linux/clk-provider.h> #include <linux/mfd/dbx500-prcmu.h> #include <linux/platform_data/clk-ux500.h> -#include <mach/db8500-regs.h> #include "clk.h" -void u8500_clk_init(void) +void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, + u32 clkrst5_base, u32 clkrst6_base) { struct prcmu_fw_version *fw_version; const char *sgaclk_parent = NULL; @@ -215,147 +215,147 @@ void u8500_clk_init(void) */ /* PRCC P-clocks */ - clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base, BIT(0), 0); clk_register_clkdev(clk, "apb_pclk", "uart0"); - clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base, BIT(1), 0); clk_register_clkdev(clk, "apb_pclk", "uart1"); - clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base, BIT(2), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1"); - clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base, BIT(3), 0); clk_register_clkdev(clk, "apb_pclk", "msp0"); clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.0"); - clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base, BIT(4), 0); clk_register_clkdev(clk, "apb_pclk", "msp1"); clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.1"); - clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base, BIT(5), 0); clk_register_clkdev(clk, "apb_pclk", "sdi0"); - clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base, BIT(6), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2"); - clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base, BIT(7), 0); clk_register_clkdev(clk, NULL, "spi3"); - clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base, BIT(8), 0); clk_register_clkdev(clk, "apb_pclk", "slimbus0"); - clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base, BIT(9), 0); clk_register_clkdev(clk, NULL, "gpio.0"); clk_register_clkdev(clk, NULL, "gpio.1"); clk_register_clkdev(clk, NULL, "gpioblock0"); - clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base, BIT(10), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4"); - clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", U8500_CLKRST1_BASE, + clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base, BIT(11), 0); clk_register_clkdev(clk, "apb_pclk", "msp3"); clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.3"); - clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base, BIT(0), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3"); - clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base, BIT(1), 0); clk_register_clkdev(clk, NULL, "spi2"); - clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base, BIT(2), 0); clk_register_clkdev(clk, NULL, "spi1"); - clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base, BIT(3), 0); clk_register_clkdev(clk, NULL, "pwl"); - clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base, BIT(4), 0); clk_register_clkdev(clk, "apb_pclk", "sdi4"); - clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base, BIT(5), 0); clk_register_clkdev(clk, "apb_pclk", "msp2"); clk_register_clkdev(clk, "apb_pclk", "ux500-msp-i2s.2"); - clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base, BIT(6), 0); clk_register_clkdev(clk, "apb_pclk", "sdi1"); - clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base, BIT(7), 0); clk_register_clkdev(clk, "apb_pclk", "sdi3"); - clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base, BIT(8), 0); clk_register_clkdev(clk, NULL, "spi0"); - clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base, BIT(9), 0); clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); - clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base, BIT(10), 0); clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); - clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base, BIT(11), 0); clk_register_clkdev(clk, NULL, "gpio.6"); clk_register_clkdev(clk, NULL, "gpio.7"); clk_register_clkdev(clk, NULL, "gpioblock1"); - clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE, + clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base, BIT(12), 0); - clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, + clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base, BIT(0), 0); clk_register_clkdev(clk, NULL, "fsmc"); - clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE, + clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base, BIT(1), 0); clk_register_clkdev(clk, "apb_pclk", "ssp0"); - clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", U8500_CLKRST3_BASE, + clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base, BIT(2), 0); clk_register_clkdev(clk, "apb_pclk", "ssp1"); - clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", U8500_CLKRST3_BASE, + clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base, BIT(3), 0); clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0"); - clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", U8500_CLKRST3_BASE, + clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base, BIT(4), 0); clk_register_clkdev(clk, "apb_pclk", "sdi2"); - clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE, + clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base, BIT(5), 0); clk_register_clkdev(clk, "apb_pclk", "ske"); clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad"); - clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE, + clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base, BIT(6), 0); clk_register_clkdev(clk, "apb_pclk", "uart2"); - clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", U8500_CLKRST3_BASE, + clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base, BIT(7), 0); clk_register_clkdev(clk, "apb_pclk", "sdi5"); - clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", U8500_CLKRST3_BASE, + clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base, BIT(8), 0); clk_register_clkdev(clk, NULL, "gpio.2"); clk_register_clkdev(clk, NULL, "gpio.3"); @@ -363,45 +363,45 @@ void u8500_clk_init(void) clk_register_clkdev(clk, NULL, "gpio.5"); clk_register_clkdev(clk, NULL, "gpioblock2"); - clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", U8500_CLKRST5_BASE, + clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base, BIT(0), 0); clk_register_clkdev(clk, "usb", "musb-ux500.0"); - clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", U8500_CLKRST5_BASE, + clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base, BIT(1), 0); clk_register_clkdev(clk, NULL, "gpio.8"); clk_register_clkdev(clk, NULL, "gpioblock3"); - clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE, + clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base, BIT(0), 0); clk_register_clkdev(clk, "apb_pclk", "rng"); - clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE, + clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base, BIT(1), 0); clk_register_clkdev(clk, NULL, "cryp0"); clk_register_clkdev(clk, NULL, "cryp1"); - clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", U8500_CLKRST6_BASE, + clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base, BIT(2), 0); clk_register_clkdev(clk, NULL, "hash0"); - clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", U8500_CLKRST6_BASE, + clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base, BIT(3), 0); clk_register_clkdev(clk, NULL, "pka"); - clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", U8500_CLKRST6_BASE, + clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base, BIT(4), 0); clk_register_clkdev(clk, NULL, "hash1"); - clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", U8500_CLKRST6_BASE, + clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base, BIT(5), 0); clk_register_clkdev(clk, NULL, "cfgreg"); - clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", U8500_CLKRST6_BASE, + clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base, BIT(6), 0); clk_register_clkdev(clk, "apb_pclk", "mtu0"); - clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", U8500_CLKRST6_BASE, + clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base, BIT(7), 0); clk_register_clkdev(clk, "apb_pclk", "mtu1"); @@ -415,110 +415,110 @@ void u8500_clk_init(void) /* Periph1 */ clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", - U8500_CLKRST1_BASE, BIT(0), CLK_SET_RATE_GATE); + clkrst1_base, BIT(0), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "uart0"); clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", - U8500_CLKRST1_BASE, BIT(1), CLK_SET_RATE_GATE); + clkrst1_base, BIT(1), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "uart1"); clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", - U8500_CLKRST1_BASE, BIT(2), CLK_SET_RATE_GATE); + clkrst1_base, BIT(2), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.1"); clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", - U8500_CLKRST1_BASE, BIT(3), CLK_SET_RATE_GATE); + clkrst1_base, BIT(3), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "msp0"); clk_register_clkdev(clk, NULL, "ux500-msp-i2s.0"); clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", - U8500_CLKRST1_BASE, BIT(4), CLK_SET_RATE_GATE); + clkrst1_base, BIT(4), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "msp1"); clk_register_clkdev(clk, NULL, "ux500-msp-i2s.1"); clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", - U8500_CLKRST1_BASE, BIT(5), CLK_SET_RATE_GATE); + clkrst1_base, BIT(5), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi0"); clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", - U8500_CLKRST1_BASE, BIT(6), CLK_SET_RATE_GATE); + clkrst1_base, BIT(6), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.2"); clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", - U8500_CLKRST1_BASE, BIT(8), CLK_SET_RATE_GATE); + clkrst1_base, BIT(8), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "slimbus0"); clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", - U8500_CLKRST1_BASE, BIT(9), CLK_SET_RATE_GATE); + clkrst1_base, BIT(9), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.4"); clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", - U8500_CLKRST1_BASE, BIT(10), CLK_SET_RATE_GATE); + clkrst1_base, BIT(10), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "msp3"); clk_register_clkdev(clk, NULL, "ux500-msp-i2s.3"); /* Periph2 */ clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", - U8500_CLKRST2_BASE, BIT(0), CLK_SET_RATE_GATE); + clkrst2_base, BIT(0), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.3"); clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", - U8500_CLKRST2_BASE, BIT(2), CLK_SET_RATE_GATE); + clkrst2_base, BIT(2), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi4"); clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", - U8500_CLKRST2_BASE, BIT(3), CLK_SET_RATE_GATE); + clkrst2_base, BIT(3), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "msp2"); clk_register_clkdev(clk, NULL, "ux500-msp-i2s.2"); clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", - U8500_CLKRST2_BASE, BIT(4), CLK_SET_RATE_GATE); + clkrst2_base, BIT(4), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi1"); clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", - U8500_CLKRST2_BASE, BIT(5), CLK_SET_RATE_GATE); + clkrst2_base, BIT(5), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi3"); /* Note that rate is received from parent. */ clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", - U8500_CLKRST2_BASE, BIT(6), + clkrst2_base, BIT(6), CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", - U8500_CLKRST2_BASE, BIT(7), + clkrst2_base, BIT(7), CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT); /* Periph3 */ clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", - U8500_CLKRST3_BASE, BIT(1), CLK_SET_RATE_GATE); + clkrst3_base, BIT(1), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "ssp0"); clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", - U8500_CLKRST3_BASE, BIT(2), CLK_SET_RATE_GATE); + clkrst3_base, BIT(2), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "ssp1"); clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", - U8500_CLKRST3_BASE, BIT(3), CLK_SET_RATE_GATE); + clkrst3_base, BIT(3), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "nmk-i2c.0"); clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", - U8500_CLKRST3_BASE, BIT(4), CLK_SET_RATE_GATE); + clkrst3_base, BIT(4), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi2"); clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", - U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE); + clkrst3_base, BIT(5), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "ske"); clk_register_clkdev(clk, NULL, "nmk-ske-keypad"); clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", - U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE); + clkrst3_base, BIT(6), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "uart2"); clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", - U8500_CLKRST3_BASE, BIT(7), CLK_SET_RATE_GATE); + clkrst3_base, BIT(7), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "sdi5"); /* Periph6 */ clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", - U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE); + clkrst6_base, BIT(0), CLK_SET_RATE_GATE); clk_register_clkdev(clk, NULL, "rng"); } diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c index c26c369eb9e..54f3d119d99 100644 --- a/drivers/clocksource/clksrc-dbx500-prcmu.c +++ b/drivers/clocksource/clksrc-dbx500-prcmu.c @@ -17,9 +17,6 @@ #include <asm/sched_clock.h> -#include <mach/setup.h> -#include <mach/hardware.h> - #define RATE_32K 32768 #define TIMER_MODE_CONTINOUS 0x1 diff --git a/drivers/crypto/ux500/cryp/cryp.c b/drivers/crypto/ux500/cryp/cryp.c index e208ceaf81c..3eafa903ebc 100644 --- a/drivers/crypto/ux500/cryp/cryp.c +++ b/drivers/crypto/ux500/cryp/cryp.c @@ -12,8 +12,6 @@ #include <linux/kernel.h> #include <linux/types.h> -#include <mach/hardware.h> - #include "cryp_p.h" #include "cryp.h" diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c index 8bc5fef07e7..2809b19e3ad 100644 --- a/drivers/crypto/ux500/cryp/cryp_core.c +++ b/drivers/crypto/ux500/cryp/cryp_core.c @@ -32,7 +32,6 @@ #include <crypto/scatterwalk.h> #include <linux/platform_data/crypto-ux500.h> -#include <mach/hardware.h> #include "cryp_p.h" #include "cryp.h" diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 632c3339895..1827e9f1f87 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -32,7 +32,6 @@ #include <crypto/algapi.h> #include <linux/platform_data/crypto-ux500.h> -#include <mach/hardware.h> #include "hash_alg.h" diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 21f261bf9e9..21434beb420 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -26,7 +26,6 @@ #include <linux/fs.h> #include <linux/platform_device.h> #include <linux/uaccess.h> -#include <linux/irqchip/arm-gic.h> #include <linux/mfd/core.h> #include <linux/mfd/dbx500-prcmu.h> #include <linux/mfd/abx500/ab8500.h> @@ -34,9 +33,7 @@ #include <linux/regulator/machine.h> #include <linux/cpufreq.h> #include <linux/platform_data/ux500_wdt.h> -#include <mach/hardware.h> -#include <mach/irqs.h> -#include <mach/db8500-regs.h> +#include <linux/platform_data/db8500_thermal.h> #include "dbx500-prcmu-regs.h" /* Index of different voltages to be used when accessing AVSData */ @@ -276,8 +273,34 @@ static struct irq_domain *db8500_irq_domain; * the bits in the bit field are not. (The bits also have a tendency to move * around, to further complicate matters.) */ -#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE) +#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name)) #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name) + +#define IRQ_PRCMU_RTC 0 +#define IRQ_PRCMU_RTT0 1 +#define IRQ_PRCMU_RTT1 2 +#define IRQ_PRCMU_HSI0 3 +#define IRQ_PRCMU_HSI1 4 +#define IRQ_PRCMU_CA_WAKE 5 +#define IRQ_PRCMU_USB 6 +#define IRQ_PRCMU_ABB 7 +#define IRQ_PRCMU_ABB_FIFO 8 +#define IRQ_PRCMU_ARM 9 +#define IRQ_PRCMU_MODEM_SW_RESET_REQ 10 +#define IRQ_PRCMU_GPIO0 11 +#define IRQ_PRCMU_GPIO1 12 +#define IRQ_PRCMU_GPIO2 13 +#define IRQ_PRCMU_GPIO3 14 +#define IRQ_PRCMU_GPIO4 15 +#define IRQ_PRCMU_GPIO5 16 +#define IRQ_PRCMU_GPIO6 17 +#define IRQ_PRCMU_GPIO7 18 +#define IRQ_PRCMU_GPIO8 19 +#define IRQ_PRCMU_CA_SLEEP 20 +#define IRQ_PRCMU_HOTMON_LOW 21 +#define IRQ_PRCMU_HOTMON_HIGH 22 +#define NUM_PRCMU_WAKEUPS 23 + static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = { IRQ_ENTRY(RTC), IRQ_ENTRY(RTT0), @@ -422,9 +445,10 @@ static DEFINE_SPINLOCK(clkout_lock); /* Global var to runtime determine TCDM base for v2 or v1 */ static __iomem void *tcdm_base; +static __iomem void *prcmu_base; struct clk_mgt { - void __iomem *reg; + u32 offset; u32 pllsw; int branch; bool clk38div; @@ -599,9 +623,9 @@ int db8500_prcmu_set_display_clocks(void) while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) cpu_relax(); - writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT); - writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT); - writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT); + writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT); + writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT); + writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT); /* Release the HW semaphore. */ writel(0, PRCM_SEM); @@ -613,7 +637,7 @@ int db8500_prcmu_set_display_clocks(void) u32 db8500_prcmu_read(unsigned int reg) { - return readl(_PRCMU_BASE + reg); + return readl(prcmu_base + reg); } void db8500_prcmu_write(unsigned int reg, u32 value) @@ -621,7 +645,7 @@ void db8500_prcmu_write(unsigned int reg, u32 value) unsigned long flags; spin_lock_irqsave(&prcmu_lock, flags); - writel(value, (_PRCMU_BASE + reg)); + writel(value, (prcmu_base + reg)); spin_unlock_irqrestore(&prcmu_lock, flags); } @@ -631,9 +655,9 @@ void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value) unsigned long flags; spin_lock_irqsave(&prcmu_lock, flags); - val = readl(_PRCMU_BASE + reg); + val = readl(prcmu_base + reg); val = ((val & ~mask) | (value & mask)); - writel(val, (_PRCMU_BASE + reg)); + writel(val, (prcmu_base + reg)); spin_unlock_irqrestore(&prcmu_lock, flags); } @@ -793,119 +817,6 @@ u8 db8500_prcmu_get_power_state_result(void) return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS); } -/* This function decouple the gic from the prcmu */ -int db8500_prcmu_gic_decouple(void) -{ - u32 val = readl(PRCM_A9_MASK_REQ); - - /* Set bit 0 register value to 1 */ - writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, - PRCM_A9_MASK_REQ); - - /* Make sure the register is updated */ - readl(PRCM_A9_MASK_REQ); - - /* Wait a few cycles for the gic mask completion */ - udelay(1); - - return 0; -} - -/* This function recouple the gic with the prcmu */ -int db8500_prcmu_gic_recouple(void) -{ - u32 val = readl(PRCM_A9_MASK_REQ); - - /* Set bit 0 register value to 0 */ - writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ); - - return 0; -} - -#define PRCMU_GIC_NUMBER_REGS 5 - -/* - * This function checks if there are pending irq on the gic. It only - * makes sense if the gic has been decoupled before with the - * db8500_prcmu_gic_decouple function. Disabling an interrupt only - * disables the forwarding of the interrupt to any CPU interface. It - * does not prevent the interrupt from changing state, for example - * becoming pending, or active and pending if it is already - * active. Hence, we have to check the interrupt is pending *and* is - * active. - */ -bool db8500_prcmu_gic_pending_irq(void) -{ - u32 pr; /* Pending register */ - u32 er; /* Enable register */ - void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); - int i; - - /* 5 registers. STI & PPI not skipped */ - for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) { - - pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); - er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); - - if (pr & er) - return true; /* There is a pending interrupt */ - } - - return false; -} - -/* - * This function checks if there are pending interrupt on the - * prcmu which has been delegated to monitor the irqs with the - * db8500_prcmu_copy_gic_settings function. - */ -bool db8500_prcmu_pending_irq(void) -{ - u32 it, im; - int i; - - for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { - it = readl(PRCM_ARMITVAL31TO0 + i * 4); - im = readl(PRCM_ARMITMSK31TO0 + i * 4); - if (it & im) - return true; /* There is a pending interrupt */ - } - - return false; -} - -/* - * This function checks if the specified cpu is in in WFI. It's usage - * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple - * function. Of course passing smp_processor_id() to this function will - * always return false... - */ -bool db8500_prcmu_is_cpu_in_wfi(int cpu) -{ - return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : - PRCM_ARM_WFI_STANDBY_WFI0; -} - -/* - * This function copies the gic SPI settings to the prcmu in order to - * monitor them and abort/finish the retention/off sequence or state. - */ -int db8500_prcmu_copy_gic_settings(void) -{ - u32 er; /* Enable register */ - void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE); - int i; - - /* We skip the STI and PPI */ - for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) { - er = readl_relaxed(dist_base + - GIC_DIST_ENABLE_SET + (i + 1) * 4); - writel(er, PRCM_ARMITMSK31TO0 + i * 4); - } - - return 0; -} - /* This function should only be called while mb0_transfer.lock is held. */ static void config_wakeups(void) { @@ -1059,7 +970,7 @@ int db8500_prcmu_set_ddr_opp(u8 opp) /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */ static void request_even_slower_clocks(bool enable) { - void __iomem *clock_reg[] = { + u32 clock_reg[] = { PRCM_ACLK_MGT, PRCM_DMACLK_MGT }; @@ -1076,7 +987,7 @@ static void request_even_slower_clocks(bool enable) u32 val; u32 div; - val = readl(clock_reg[i]); + val = readl(prcmu_base + clock_reg[i]); div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK); if (enable) { if ((div <= 1) || (div > 15)) { @@ -1092,7 +1003,7 @@ static void request_even_slower_clocks(bool enable) } val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) | (div & PRCM_CLK_MGT_CLKPLLDIV_MASK)); - writel(val, clock_reg[i]); + writel(val, prcmu_base + clock_reg[i]); } unlock_and_return: @@ -1446,14 +1357,14 @@ static int request_clock(u8 clock, bool enable) while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) cpu_relax(); - val = readl(clk_mgt[clock].reg); + val = readl(prcmu_base + clk_mgt[clock].offset); if (enable) { val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); } else { clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK); } - writel(val, clk_mgt[clock].reg); + writel(val, prcmu_base + clk_mgt[clock].offset); /* Release the HW semaphore. */ writel(0, PRCM_SEM); @@ -1629,7 +1540,7 @@ static unsigned long clock_rate(u8 clock) u32 pllsw; unsigned long rate = ROOT_CLOCK_RATE; - val = readl(clk_mgt[clock].reg); + val = readl(prcmu_base + clk_mgt[clock].offset); if (val & PRCM_CLK_MGT_CLK38) { if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) @@ -1785,7 +1696,7 @@ static long round_clock_rate(u8 clock, unsigned long rate) unsigned long src_rate; long rounded_rate; - val = readl(clk_mgt[clock].reg); + val = readl(prcmu_base + clk_mgt[clock].offset); src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), clk_mgt[clock].branch); div = clock_divider(src_rate, rate); @@ -1933,7 +1844,7 @@ static void set_clock_rate(u8 clock, unsigned long rate) while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) cpu_relax(); - val = readl(clk_mgt[clock].reg); + val = readl(prcmu_base + clk_mgt[clock].offset); src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), clk_mgt[clock].branch); div = clock_divider(src_rate, rate); @@ -1961,7 +1872,7 @@ static void set_clock_rate(u8 clock, unsigned long rate) val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK; val |= min(div, (u32)31); } - writel(val, clk_mgt[clock].reg); + writel(val, prcmu_base + clk_mgt[clock].offset); /* Release the HW semaphore. */ writel(0, PRCM_SEM); @@ -2764,14 +2675,13 @@ static struct irq_domain_ops db8500_irq_ops = { .xlate = irq_domain_xlate_twocell, }; -static int db8500_irq_init(struct device_node *np) +static int db8500_irq_init(struct device_node *np, int irq_base) { - int irq_base = 0; int i; /* In the device tree case, just take some IRQs */ - if (!np) - irq_base = IRQ_PRCMU_BASE; + if (np) + irq_base = 0; db8500_irq_domain = irq_domain_add_simple( np, NUM_PRCMU_WAKEUPS, irq_base, @@ -2825,8 +2735,19 @@ static void dbx500_fw_version_init(struct platform_device *pdev, } } -void __init db8500_prcmu_early_init(void) +void __init db8500_prcmu_early_init(u32 phy_base, u32 size) { + /* + * This is a temporary remap to bring up the clocks. It is + * subsequently replaces with a real remap. After the merge of + * the mailbox subsystem all of this early code goes away, and the + * clock driver can probe independently. An early initcall will + * still be needed, but it can be diverted into drivers/clk/ux500. + */ + prcmu_base = ioremap(phy_base, size); + if (!prcmu_base) + pr_err("%s: ioremap() of prcmu registers failed!\n", __func__); + spin_lock_init(&mb0_transfer.lock); spin_lock_init(&mb0_transfer.dbb_irqs_lock); mutex_init(&mb0_transfer.ac_wake_lock); @@ -3092,18 +3013,57 @@ static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = { }, }; -static struct resource ab8500_resources[] = { - [0] = { - .start = IRQ_DB8500_AB8500, - .end = IRQ_DB8500_AB8500, - .flags = IORESOURCE_IRQ - } -}; - static struct ux500_wdt_data db8500_wdt_pdata = { .timeout = 600, /* 10 minutes */ .has_28_bits_resolution = true, }; +/* + * Thermal Sensor + */ + +static struct resource db8500_thsens_resources[] = { + { + .name = "IRQ_HOTMON_LOW", + .start = IRQ_PRCMU_HOTMON_LOW, + .end = IRQ_PRCMU_HOTMON_LOW, + .flags = IORESOURCE_IRQ, + }, + { + .name = "IRQ_HOTMON_HIGH", + .start = IRQ_PRCMU_HOTMON_HIGH, + .end = IRQ_PRCMU_HOTMON_HIGH, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct db8500_thsens_platform_data db8500_thsens_data = { + .trip_points[0] = { + .temp = 70000, + .type = THERMAL_TRIP_ACTIVE, + .cdev_name = { + [0] = "thermal-cpufreq-0", + }, + }, + .trip_points[1] = { + .temp = 75000, + .type = THERMAL_TRIP_ACTIVE, + .cdev_name = { + [0] = "thermal-cpufreq-0", + }, + }, + .trip_points[2] = { + .temp = 80000, + .type = THERMAL_TRIP_ACTIVE, + .cdev_name = { + [0] = "thermal-cpufreq-0", + }, + }, + .trip_points[3] = { + .temp = 85000, + .type = THERMAL_TRIP_CRITICAL, + }, + .num_trips = 4, +}; static struct mfd_cell db8500_prcmu_devs[] = { { @@ -3125,11 +3085,10 @@ static struct mfd_cell db8500_prcmu_devs[] = { .id = -1, }, { - .name = "ab8500-core", - .of_compatible = "stericsson,ab8500", - .num_resources = ARRAY_SIZE(ab8500_resources), - .resources = ab8500_resources, - .id = AB8500_VERSION_AB8500, + .name = "db8500-thermal", + .num_resources = ARRAY_SIZE(db8500_thsens_resources), + .resources = db8500_thsens_resources, + .platform_data = &db8500_thsens_data, }, }; @@ -3141,6 +3100,24 @@ static void db8500_prcmu_update_cpufreq(void) } } +static int db8500_prcmu_register_ab8500(struct device *parent, + struct ab8500_platform_data *pdata, + int irq) +{ + struct resource ab8500_resource = DEFINE_RES_IRQ(irq); + struct mfd_cell ab8500_cell = { + .name = "ab8500-core", + .of_compatible = "stericsson,ab8500", + .id = AB8500_VERSION_AB8500, + .platform_data = pdata, + .pdata_size = sizeof(struct ab8500_platform_data), + .resources = &ab8500_resource, + .num_resources = 1, + }; + + return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL); +} + /** * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic * @@ -3149,11 +3126,21 @@ static int db8500_prcmu_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev); - int irq = 0, err = 0, i; + int irq = 0, err = 0; struct resource *res; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu"); + if (!res) { + dev_err(&pdev->dev, "no prcmu memory region provided\n"); + return -ENOENT; + } + prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!prcmu_base) { + dev_err(&pdev->dev, + "failed to ioremap prcmu register memory\n"); + return -ENOENT; + } init_prcm_registers(); - dbx500_fw_version_init(pdev, pdata->version_offset); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm"); if (!res) { @@ -3180,26 +3167,27 @@ static int db8500_prcmu_probe(struct platform_device *pdev) goto no_irq_return; } - db8500_irq_init(np); - - for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) { - if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) { - db8500_prcmu_devs[i].platform_data = pdata->ab_platdata; - db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data); - } - } + db8500_irq_init(np, pdata->irq_base); prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); db8500_prcmu_update_cpufreq(); err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, - ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL); + ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, db8500_irq_domain); if (err) { pr_err("prcmu: Failed to add subdevices\n"); return err; } + err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata, + pdata->ab_irq); + if (err) { + mfd_remove_devices(&pdev->dev); + pr_err("prcmu: Failed to add ab8500 subdevice\n"); + goto no_irq_return; + } + pr_info("DB8500 PRCMU initialized\n"); no_irq_return: diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h index 79c76ebdba5..d14836ed211 100644 --- a/drivers/mfd/dbx500-prcmu-regs.h +++ b/drivers/mfd/dbx500-prcmu-regs.h @@ -13,136 +13,110 @@ #ifndef __DB8500_PRCMU_REGS_H #define __DB8500_PRCMU_REGS_H -#include <mach/hardware.h> - #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) -#define PRCM_CLK_MGT(_offset) (void __iomem *)(IO_ADDRESS(U8500_PRCMU_BASE) \ - + _offset) -#define PRCM_ACLK_MGT PRCM_CLK_MGT(0x004) -#define PRCM_SVACLK_MGT PRCM_CLK_MGT(0x008) -#define PRCM_SIACLK_MGT PRCM_CLK_MGT(0x00C) -#define PRCM_SGACLK_MGT PRCM_CLK_MGT(0x014) -#define PRCM_UARTCLK_MGT PRCM_CLK_MGT(0x018) -#define PRCM_MSP02CLK_MGT PRCM_CLK_MGT(0x01C) -#define PRCM_I2CCLK_MGT PRCM_CLK_MGT(0x020) -#define PRCM_SDMMCCLK_MGT PRCM_CLK_MGT(0x024) -#define PRCM_SLIMCLK_MGT PRCM_CLK_MGT(0x028) -#define PRCM_PER1CLK_MGT PRCM_CLK_MGT(0x02C) -#define PRCM_PER2CLK_MGT PRCM_CLK_MGT(0x030) -#define PRCM_PER3CLK_MGT PRCM_CLK_MGT(0x034) -#define PRCM_PER5CLK_MGT PRCM_CLK_MGT(0x038) -#define PRCM_PER6CLK_MGT PRCM_CLK_MGT(0x03C) -#define PRCM_PER7CLK_MGT PRCM_CLK_MGT(0x040) -#define PRCM_LCDCLK_MGT PRCM_CLK_MGT(0x044) -#define PRCM_BMLCLK_MGT PRCM_CLK_MGT(0x04C) -#define PRCM_HSITXCLK_MGT PRCM_CLK_MGT(0x050) -#define PRCM_HSIRXCLK_MGT PRCM_CLK_MGT(0x054) -#define PRCM_HDMICLK_MGT PRCM_CLK_MGT(0x058) -#define PRCM_APEATCLK_MGT PRCM_CLK_MGT(0x05C) -#define PRCM_APETRACECLK_MGT PRCM_CLK_MGT(0x060) -#define PRCM_MCDECLK_MGT PRCM_CLK_MGT(0x064) -#define PRCM_IPI2CCLK_MGT PRCM_CLK_MGT(0x068) -#define PRCM_DSIALTCLK_MGT PRCM_CLK_MGT(0x06C) -#define PRCM_DMACLK_MGT PRCM_CLK_MGT(0x074) -#define PRCM_B2R2CLK_MGT PRCM_CLK_MGT(0x078) -#define PRCM_TVCLK_MGT PRCM_CLK_MGT(0x07C) -#define PRCM_UNIPROCLK_MGT PRCM_CLK_MGT(0x278) -#define PRCM_SSPCLK_MGT PRCM_CLK_MGT(0x280) -#define PRCM_RNGCLK_MGT PRCM_CLK_MGT(0x284) -#define PRCM_UICCCLK_MGT PRCM_CLK_MGT(0x27C) -#define PRCM_MSP1CLK_MGT PRCM_CLK_MGT(0x288) - -#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118) +#define PRCM_ACLK_MGT (0x004) +#define PRCM_SVACLK_MGT (0x008) +#define PRCM_SIACLK_MGT (0x00C) +#define PRCM_SGACLK_MGT (0x014) +#define PRCM_UARTCLK_MGT (0x018) +#define PRCM_MSP02CLK_MGT (0x01C) +#define PRCM_I2CCLK_MGT (0x020) +#define PRCM_SDMMCCLK_MGT (0x024) +#define PRCM_SLIMCLK_MGT (0x028) +#define PRCM_PER1CLK_MGT (0x02C) +#define PRCM_PER2CLK_MGT (0x030) +#define PRCM_PER3CLK_MGT (0x034) +#define PRCM_PER5CLK_MGT (0x038) +#define PRCM_PER6CLK_MGT (0x03C) +#define PRCM_PER7CLK_MGT (0x040) +#define PRCM_LCDCLK_MGT (0x044) +#define PRCM_BMLCLK_MGT (0x04C) +#define PRCM_HSITXCLK_MGT (0x050) +#define PRCM_HSIRXCLK_MGT (0x054) +#define PRCM_HDMICLK_MGT (0x058) +#define PRCM_APEATCLK_MGT (0x05C) +#define PRCM_APETRACECLK_MGT (0x060) +#define PRCM_MCDECLK_MGT (0x064) +#define PRCM_IPI2CCLK_MGT (0x068) +#define PRCM_DSIALTCLK_MGT (0x06C) +#define PRCM_DMACLK_MGT (0x074) +#define PRCM_B2R2CLK_MGT (0x078) +#define PRCM_TVCLK_MGT (0x07C) +#define PRCM_UNIPROCLK_MGT (0x278) +#define PRCM_SSPCLK_MGT (0x280) +#define PRCM_RNGCLK_MGT (0x284) +#define PRCM_UICCCLK_MGT (0x27C) +#define PRCM_MSP1CLK_MGT (0x288) + +#define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118) #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f #define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf -#define PRCM_PLLARM_LOCKP (_PRCMU_BASE + 0x0a8) +#define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8) #define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 -#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) +#define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114) #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) #define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) -#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) +#define PRCM_PLLARM_ENABLE (prcmu_base + 0x98) #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100 -#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0) -#define PRCM_A9PL_FORCE_CLKEN (_PRCMU_BASE + 0x19C) -#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4) -#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0) -#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c) -#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308) +#define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0) +#define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C) +#define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4) +#define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0) +#define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c) +#define PRCM_SRAM_A9 (prcmu_base + 0x308) #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0) #define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1) -/* ARM WFI Standby signal register */ -#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130) -#define PRCM_ARM_WFI_STANDBY_WFI0 0x08 -#define PRCM_ARM_WFI_STANDBY_WFI1 0x10 -#define PRCM_IOCR (_PRCMU_BASE + 0x310) -#define PRCM_IOCR_IOFORCE 0x1 - /* CPU mailbox registers */ -#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc) -#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100) -#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104) - -/* Dual A9 core interrupt management unit registers */ -#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328) -#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1 - -#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c) -#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c) -#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120) -#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124) -#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128) -#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C) -#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260) -#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264) -#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268) -#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C) - -#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334) +#define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc) +#define PRCM_MBOX_CPU_SET (prcmu_base + 0x100) +#define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104) + +#define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334) #define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1 #define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16) #define ARM_WAKEUP_MODEM 0x1 -#define PRCM_ARM_IT1_CLR (_PRCMU_BASE + 0x48C) -#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494) -#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174) +#define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C) +#define PRCM_ARM_IT1_VAL (prcmu_base + 0x494) +#define PRCM_HOLD_EVT (prcmu_base + 0x174) -#define PRCM_MOD_AWAKE_STATUS (_PRCMU_BASE + 0x4A0) +#define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0) #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0) #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1) #define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2) -#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148) -#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150) -#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158) -#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160) -#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168) -#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484) -#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488) -#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018) +#define PRCM_ITSTATUS0 (prcmu_base + 0x148) +#define PRCM_ITSTATUS1 (prcmu_base + 0x150) +#define PRCM_ITSTATUS2 (prcmu_base + 0x158) +#define PRCM_ITSTATUS3 (prcmu_base + 0x160) +#define PRCM_ITSTATUS4 (prcmu_base + 0x168) +#define PRCM_ITSTATUS5 (prcmu_base + 0x484) +#define PRCM_ITCLEAR5 (prcmu_base + 0x488) +#define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018) /* System reset register */ -#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) +#define PRCM_APE_SOFTRST (prcmu_base + 0x228) /* Level shifter and clamp control registers */ -#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420) -#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) +#define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420) +#define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424) #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11) #define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22) /* PRCMU clock/PLL/reset registers */ -#define PRCM_PLLSOC0_FREQ (_PRCMU_BASE + 0x080) -#define PRCM_PLLSOC1_FREQ (_PRCMU_BASE + 0x084) -#define PRCM_PLLARM_FREQ (_PRCMU_BASE + 0x088) -#define PRCM_PLLDDR_FREQ (_PRCMU_BASE + 0x08C) +#define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080) +#define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084) +#define PRCM_PLLARM_FREQ (prcmu_base + 0x088) +#define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C) #define PRCM_PLL_FREQ_D_SHIFT 0 #define PRCM_PLL_FREQ_D_MASK BITS(0, 7) #define PRCM_PLL_FREQ_N_SHIFT 8 @@ -152,14 +126,14 @@ #define PRCM_PLL_FREQ_SELDIV2 BIT(24) #define PRCM_PLL_FREQ_DIV2EN BIT(25) -#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) -#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) -#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) -#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530) -#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C) -#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) -#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) -#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) +#define PRCM_PLLDSI_FREQ (prcmu_base + 0x500) +#define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504) +#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) +#define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530) +#define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C) +#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) +#define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4) +#define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8) #define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0) @@ -188,30 +162,30 @@ #define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14) -#define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC) +#define PRCM_CLKOCR (prcmu_base + 0x1CC) #define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) #define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) #define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16) #define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29) /* ePOD and memory power signal control registers */ -#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410) -#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304) +#define PRCM_EPOD_C_SET (prcmu_base + 0x410) +#define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304) /* Debug power control unit registers */ -#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254) +#define PRCM_POWER_STATE_SET (prcmu_base + 0x254) /* Miscellaneous unit registers */ -#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) -#define PRCM_GPIOCR (_PRCMU_BASE + 0x138) +#define PRCM_DSI_SW_RESET (prcmu_base + 0x324) +#define PRCM_GPIOCR (prcmu_base + 0x138) #define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800 #define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1 /* PRCMU HW semaphore */ -#define PRCM_SEM (_PRCMU_BASE + 0x400) +#define PRCM_SEM (prcmu_base + 0x400) #define PRCM_SEM_PRCM_SEM BIT(0) -#define PRCM_TCR (_PRCMU_BASE + 0x1C8) +#define PRCM_TCR (prcmu_base + 0x1C8) #define PRCM_TCR_TENSEL_MASK BITS(0, 7) #define PRCM_TCR_STOP_TIMERS BIT(16) #define PRCM_TCR_DOZE_MODE BIT(17) @@ -239,15 +213,15 @@ /* GPIOCR register */ #define PRCM_GPIOCR_SPI2_SELECT BIT(23) -#define PRCM_DDR_SUBSYS_APE_MINBW (_PRCMU_BASE + 0x438) -#define PRCM_CGATING_BYPASS (_PRCMU_BASE + 0x134) +#define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438) +#define PRCM_CGATING_BYPASS (prcmu_base + 0x134) #define PRCM_CGATING_BYPASS_ICN2 BIT(6) /* Miscellaneous unit registers */ -#define PRCM_RESOUTN_SET (_PRCMU_BASE + 0x214) -#define PRCM_RESOUTN_CLR (_PRCMU_BASE + 0x218) +#define PRCM_RESOUTN_SET (prcmu_base + 0x214) +#define PRCM_RESOUTN_CLR (prcmu_base + 0x218) /* System reset register */ -#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) +#define PRCM_APE_SOFTRST (prcmu_base + 0x228) #endif /* __DB8500_PRCMU_REGS_H */ diff --git a/drivers/staging/ste_rmi4/Makefile b/drivers/staging/ste_rmi4/Makefile index e4c03351420..6cce2ed187e 100644 --- a/drivers/staging/ste_rmi4/Makefile +++ b/drivers/staging/ste_rmi4/Makefile @@ -2,4 +2,3 @@ # Makefile for the RMI4 touchscreen driver. # obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) += synaptics_i2c_rmi4.o -obj-$(CONFIG_MACH_MOP500) += board-mop500-u8500uib-rmi4.o diff --git a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c b/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c deleted file mode 100644 index 47439c3f725..00000000000 --- a/drivers/staging/ste_rmi4/board-mop500-u8500uib-rmi4.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Some platform data for the RMI4 touchscreen that will override the __weak - * platform data in the Ux500 machine if this driver is activated. - */ -#include <linux/i2c.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <mach/irqs.h> -#include "synaptics_i2c_rmi4.h" - -/* - * Synaptics RMI4 touchscreen interface on the U8500 UIB - */ - -/* - * Descriptor structure. - * Describes the number of i2c devices on the bus that speak RMI. - */ -static struct synaptics_rmi4_platform_data rmi4_i2c_dev_platformdata = { - .irq_number = NOMADIK_GPIO_TO_IRQ(84), - .irq_type = (IRQF_TRIGGER_FALLING | IRQF_SHARED), - .x_flip = false, - .y_flip = true, -}; - -struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = { - { - I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B), - .platform_data = &rmi4_i2c_dev_platformdata, - }, -}; diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c index 6a21f67af08..2e3530736bc 100644 --- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c +++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.c @@ -864,6 +864,16 @@ static int synaptics_rmi4_i2c_query_device(struct synaptics_rmi4_data *pdata) return 0; } +/* + * Descriptor structure. + * Describes the number of i2c devices on the bus that speak RMI. + */ +static struct synaptics_rmi4_platform_data synaptics_rmi4_platformdata = { + .irq_type = (IRQF_TRIGGER_FALLING | IRQF_SHARED), + .x_flip = false, + .y_flip = true, +}; + /** * synaptics_rmi4_probe() - Initialze the i2c-client touchscreen driver * @i2c: i2c client structure pointer @@ -890,10 +900,8 @@ static int synaptics_rmi4_probe return -EIO; } - if (!platformdata) { - dev_err(&client->dev, "%s: no platform data\n", __func__); - return -EINVAL; - } + if (!platformdata) + platformdata = &synaptics_rmi4_platformdata; /* Allocate and initialize the instance data for this client */ rmi4_data = kcalloc(2, sizeof(struct synaptics_rmi4_data), @@ -977,13 +985,13 @@ static int synaptics_rmi4_probe synaptics_rmi4_i2c_block_read(rmi4_data, rmi4_data->fn01_data_base_addr + 1, intr_status, rmi4_data->number_of_interrupt_register); - retval = request_threaded_irq(platformdata->irq_number, NULL, + retval = request_threaded_irq(client->irq, NULL, synaptics_rmi4_irq, platformdata->irq_type, DRIVER_NAME, rmi4_data); if (retval) { dev_err(&client->dev, "%s:Unable to get attn irq %d\n", - __func__, platformdata->irq_number); + __func__, client->irq); goto err_query_dev; } @@ -996,7 +1004,7 @@ static int synaptics_rmi4_probe return retval; err_free_irq: - free_irq(platformdata->irq_number, rmi4_data); + free_irq(client->irq, rmi4_data); err_query_dev: regulator_disable(rmi4_data->regulator); err_regulator_enable: @@ -1019,11 +1027,10 @@ err_input: static int synaptics_rmi4_remove(struct i2c_client *client) { struct synaptics_rmi4_data *rmi4_data = i2c_get_clientdata(client); - const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board; rmi4_data->touch_stopped = true; wake_up(&rmi4_data->wait); - free_irq(pdata->irq_number, rmi4_data); + free_irq(client->irq, rmi4_data); input_unregister_device(rmi4_data->input_dev); regulator_disable(rmi4_data->regulator); regulator_put(rmi4_data->regulator); @@ -1046,10 +1053,9 @@ static int synaptics_rmi4_suspend(struct device *dev) int retval; unsigned char intr_status; struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev); - const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board; rmi4_data->touch_stopped = true; - disable_irq(pdata->irq_number); + disable_irq(rmi4_data->i2c_client->irq); retval = synaptics_rmi4_i2c_block_read(rmi4_data, rmi4_data->fn01_data_base_addr + 1, @@ -1080,11 +1086,10 @@ static int synaptics_rmi4_resume(struct device *dev) int retval; unsigned char intr_status; struct synaptics_rmi4_data *rmi4_data = dev_get_drvdata(dev); - const struct synaptics_rmi4_platform_data *pdata = rmi4_data->board; regulator_enable(rmi4_data->regulator); - enable_irq(pdata->irq_number); + enable_irq(rmi4_data->i2c_client->irq); rmi4_data->touch_stopped = false; retval = synaptics_rmi4_i2c_block_read(rmi4_data, diff --git a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h index 384436ef806..8c9166ba71c 100644 --- a/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h +++ b/drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h @@ -38,7 +38,6 @@ * This structure gives platform data for rmi4. */ struct synaptics_rmi4_platform_data { - int irq_number; int irq_type; bool x_flip; bool y_flip; diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h index 77a46ae2fc1..0bd69446bb0 100644 --- a/include/linux/mfd/db8500-prcmu.h +++ b/include/linux/mfd/db8500-prcmu.h @@ -489,7 +489,7 @@ struct prcmu_auto_pm_config { #ifdef CONFIG_MFD_DB8500_PRCMU -void db8500_prcmu_early_init(void); +void db8500_prcmu_early_init(u32 phy_base, u32 size); int prcmu_set_rc_a2p(enum romcode_write); enum romcode_read prcmu_get_rc_p2a(void); enum ap_pwrst prcmu_get_xp70_current_state(void); @@ -522,12 +522,6 @@ int db8500_prcmu_load_a9wdog(u8 id, u32 val); void db8500_prcmu_system_reset(u16 reset_code); int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); u8 db8500_prcmu_get_power_state_result(void); -int db8500_prcmu_gic_decouple(void); -int db8500_prcmu_gic_recouple(void); -int db8500_prcmu_copy_gic_settings(void); -bool db8500_prcmu_gic_pending_irq(void); -bool db8500_prcmu_pending_irq(void); -bool db8500_prcmu_is_cpu_in_wfi(int cpu); void db8500_prcmu_enable_wakeups(u32 wakeups); int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state); int db8500_prcmu_request_clock(u8 clock, bool enable); @@ -553,7 +547,7 @@ void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value); #else /* !CONFIG_MFD_DB8500_PRCMU */ -static inline void db8500_prcmu_early_init(void) {} +static inline void db8500_prcmu_early_init(u32 phy_base, u32 size) {} static inline int prcmu_set_rc_a2p(enum romcode_write code) { diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index 3abcca91eec..689e6a0d9c9 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -237,6 +237,8 @@ struct prcmu_pdata bool enable_set_ddr_opp; bool enable_ape_opp_100_voltage; struct ab8500_platform_data *ab_platdata; + int ab_irq; + int irq_base; u32 version_offset; u32 legacy_offset; u32 adt_offset; @@ -276,9 +278,9 @@ struct prcmu_fw_version { #if defined(CONFIG_UX500_SOC_DB8500) -static inline void __init prcmu_early_init(void) +static inline void prcmu_early_init(u32 phy_base, u32 size) { - return db8500_prcmu_early_init(); + return db8500_prcmu_early_init(phy_base, size); } static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, @@ -293,36 +295,6 @@ static inline u8 prcmu_get_power_state_result(void) return db8500_prcmu_get_power_state_result(); } -static inline int prcmu_gic_decouple(void) -{ - return db8500_prcmu_gic_decouple(); -} - -static inline int prcmu_gic_recouple(void) -{ - return db8500_prcmu_gic_recouple(); -} - -static inline bool prcmu_gic_pending_irq(void) -{ - return db8500_prcmu_gic_pending_irq(); -} - -static inline bool prcmu_is_cpu_in_wfi(int cpu) -{ - return db8500_prcmu_is_cpu_in_wfi(cpu); -} - -static inline int prcmu_copy_gic_settings(void) -{ - return db8500_prcmu_copy_gic_settings(); -} - -static inline bool prcmu_pending_irq(void) -{ - return db8500_prcmu_pending_irq(); -} - static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) { return db8500_prcmu_set_epod(epod_id, epod_state); @@ -500,7 +472,7 @@ static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) } #else -static inline void __init prcmu_early_init(void) {} +static inline void prcmu_early_init(u32 phy_base, u32 size) {} static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) diff --git a/include/linux/platform_data/arm-ux500-pm.h b/include/linux/platform_data/arm-ux500-pm.h new file mode 100644 index 00000000000..8dff64b29ec --- /dev/null +++ b/include/linux/platform_data/arm-ux500-pm.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) ST-Ericsson SA 2010-2013 + * Author: Rickard Andersson <rickard.andersson@stericsson.com> for + * ST-Ericsson. + * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro. + * License terms: GNU General Public License (GPL) version 2 + * + */ + +#ifndef ARM_UX500_PM_H +#define ARM_UX500_PM_H + +int prcmu_gic_decouple(void); +int prcmu_gic_recouple(void); +bool prcmu_gic_pending_irq(void); +bool prcmu_pending_irq(void); +bool prcmu_is_cpu_in_wfi(int cpu); +int prcmu_copy_gic_settings(void); +void ux500_pm_init(u32 phy_base, u32 size); + +#endif /* ARM_UX500_PM_H */ diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/include/linux/platform_data/asoc-ux500-msp.h index 9991aea3d57..9991aea3d57 100644 --- a/arch/arm/mach-ux500/include/mach/msp.h +++ b/include/linux/platform_data/asoc-ux500-msp.h diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h index 3af0da1f3be..320d9c39ea0 100644 --- a/include/linux/platform_data/clk-ux500.h +++ b/include/linux/platform_data/clk-ux500.h @@ -10,7 +10,8 @@ #ifndef __CLK_UX500_H #define __CLK_UX500_H -void u8500_clk_init(void); +void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base, + u32 clkrst5_base, u32 clkrst6_base); void u9540_clk_init(void); void u8540_clk_init(void); diff --git a/sound/soc/ux500/mop500_ab8500.c b/sound/soc/ux500/mop500_ab8500.c index 78cce236693..892ad9a05c9 100644 --- a/sound/soc/ux500/mop500_ab8500.c +++ b/sound/soc/ux500/mop500_ab8500.c @@ -17,8 +17,6 @@ #include <linux/io.h> #include <linux/clk.h> -#include <mach/hardware.h> - #include <sound/soc.h> #include <sound/soc-dapm.h> #include <sound/pcm.h> diff --git a/sound/soc/ux500/ux500_msp_dai.c b/sound/soc/ux500/ux500_msp_dai.c index 94a3e5705aa..54028cf7651 100644 --- a/sound/soc/ux500/ux500_msp_dai.c +++ b/sound/soc/ux500/ux500_msp_dai.c @@ -19,9 +19,7 @@ #include <linux/clk.h> #include <linux/regulator/consumer.h> #include <linux/mfd/dbx500-prcmu.h> - -#include <mach/hardware.h> -#include <mach/msp.h> +#include <linux/platform_data/asoc-ux500-msp.h> #include <sound/soc.h> #include <sound/soc-dai.h> diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c index a26c6bf0a29..f2db6c90a9e 100644 --- a/sound/soc/ux500/ux500_msp_i2s.c +++ b/sound/soc/ux500/ux500_msp_i2s.c @@ -20,9 +20,7 @@ #include <linux/slab.h> #include <linux/io.h> #include <linux/of.h> - -#include <mach/hardware.h> -#include <mach/msp.h> +#include <linux/platform_data/asoc-ux500-msp.h> #include <sound/soc.h> diff --git a/sound/soc/ux500/ux500_msp_i2s.h b/sound/soc/ux500/ux500_msp_i2s.h index 1311c0df762..437f0c032c5 100644 --- a/sound/soc/ux500/ux500_msp_i2s.h +++ b/sound/soc/ux500/ux500_msp_i2s.h @@ -17,8 +17,6 @@ #include <linux/platform_device.h> -#include <mach/msp.h> - #define MSP_INPUT_FREQ_APB 48000000 /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono), |