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/*
* Copyright (C) ST-Ericsson SA 2011
*
* License Terms: GNU General Public License v2
*/
#ifndef __MACH_PRCMU_REGS_DB5500_H
#define __MACH_PRCMU_REGS_DB5500_H
#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
#define PRCM_TCR 0x1C8
#define PRCM_TCR_TENSEL_MASK BITS(0, 7)
#define PRCM_TCR_STOP_TIMERS BIT(16)
#define PRCM_TCR_DOZE_MODE BIT(17)
/* PRCMU HW semaphore */
#define PRCM_SEM 0x400
#define PRCM_SEM_PRCM_SEM BIT(0)
#define DB5500_PRCM_SVACLK_MGT 0x008
#define DB5500_PRCM_SIACLK_MGT 0x00C
#define DB5500_PRCM_SGACLK_MGT 0x014
#define DB5500_PRCM_UARTCLK_MGT 0x018
#define DB5500_PRCM_MSP02CLK_MGT 0x01C
#define DB5500_PRCM_I2CCLK_MGT 0x020
#define DB5500_PRCM_SDMMCCLK_MGT 0x024
#define DB5500_PRCM_PER1CLK_MGT 0x02C
#define DB5500_PRCM_PER2CLK_MGT 0x030
#define DB5500_PRCM_PER3CLK_MGT 0x034
#define DB5500_PRCM_PER5CLK_MGT 0x038
#define DB5500_PRCM_PER6CLK_MGT 0x03C
#define DB5500_PRCM_PWMCLK_MGT 0x044
#define DB5500_PRCM_IRDACLK_MGT 0x048
#define DB5500_PRCM_IRRCCLK_MGT 0x04C
#define DB5500_PRCM_HDMICLK_MGT 0x058
#define DB5500_PRCM_APEATCLK_MGT 0x05C
#define DB5500_PRCM_APETRACECLK_MGT 0x060
#define DB5500_PRCM_MCDECLK_MGT 0x064
#define DB5500_PRCM_DSIALTCLK_MGT 0x06C
#define DB5500_PRCM_DMACLK_MGT 0x074
#define DB5500_PRCM_B2R2CLK_MGT 0x078
#define DB5500_PRCM_TVCLK_MGT 0x07C
#define DB5500_PRCM_RNGCLK_MGT 0x284
#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4)
#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7)
#define PRCM_CLK_MGT_CLKEN BIT(8)
#define PRCM_CLKOCR 0x1CC
#define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0)
#define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13)
#define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16)
#define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29)
#define PRCM_ARM_IT1_CLEAR 0x48C
#define PRCM_ARM_IT1_VAL 0x494
/* CPU mailbox registers */
#define PRCM_MBOX_CPU_VAL 0x0FC
#define PRCM_MBOX_CPU_SET 0x100
/* System reset register */
#define PRCM_APE_SOFTRST 0x228
/* PRCMU clock/PLL/reset registers */
#define PRCM_PLLDSI_FREQ 0x500
#define PRCM_PLLDSI_ENABLE 0x504
#define PRCM_PLLDSI_LOCKP 0x508
#define PRCM_DSI_PLLOUT_SEL 0x530
#define PRCM_DSITVCLK_DIV 0x52C
#define PRCM_APE_RESETN_SET 0x1E4
#define PRCM_APE_RESETN_CLR 0x1E8
#define PRCM_MMIP_LS_CLAMP_SET 0x420
#define PRCM_MMIP_LS_CLAMP_CLR 0x424
/* Miscellaneous unit registers */
#define PRCM_DSI_SW_RESET 0x324
#define PRCM_RESOUTN_SET_OFFSET 0x214
#define PRCM_RESOUTN_CLR_OFFSET 0x218
#endif
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