diff options
Diffstat (limited to 'arch/blackfin/include/asm')
32 files changed, 629 insertions, 338 deletions
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild index 09c31418cc0..9e7c5379d3f 100644 --- a/arch/blackfin/include/asm/Kbuild +++ b/arch/blackfin/include/asm/Kbuild @@ -1,4 +1,5 @@ include include/asm-generic/Kbuild.asm -unifdef-y += bfin_sport.h -unifdef-y += fixed_code.h +header-y += bfin_sport.h +header-y += cachectl.h +header-y += fixed_code.h diff --git a/arch/blackfin/include/asm/bfin5xx_spi.h b/arch/blackfin/include/asm/bfin5xx_spi.h index ed4f8c6db0c..5392583d025 100644 --- a/arch/blackfin/include/asm/bfin5xx_spi.h +++ b/arch/blackfin/include/asm/bfin5xx_spi.h @@ -11,26 +11,17 @@ #define MIN_SPI_BAUD_VAL 2 -#define SPI_READ 0 -#define SPI_WRITE 1 - -#define SPI_CTRL_OFF 0x0 -#define SPI_FLAG_OFF 0x4 -#define SPI_STAT_OFF 0x8 -#define SPI_TXBUFF_OFF 0xc -#define SPI_RXBUFF_OFF 0x10 -#define SPI_BAUD_OFF 0x14 -#define SPI_SHAW_OFF 0x18 - - #define BIT_CTL_ENABLE 0x4000 #define BIT_CTL_OPENDRAIN 0x2000 #define BIT_CTL_MASTER 0x1000 -#define BIT_CTL_POLAR 0x0800 -#define BIT_CTL_PHASE 0x0400 -#define BIT_CTL_BITORDER 0x0200 +#define BIT_CTL_CPOL 0x0800 +#define BIT_CTL_CPHA 0x0400 +#define BIT_CTL_LSBF 0x0200 #define BIT_CTL_WORDSIZE 0x0100 -#define BIT_CTL_MISOENABLE 0x0020 +#define BIT_CTL_EMISO 0x0020 +#define BIT_CTL_PSSE 0x0010 +#define BIT_CTL_GM 0x0008 +#define BIT_CTL_SZ 0x0004 #define BIT_CTL_RXMOD 0x0000 #define BIT_CTL_TXMOD 0x0001 #define BIT_CTL_TIMOD_DMA_TX 0x0003 @@ -50,61 +41,28 @@ #define BIT_STU_SENDOVER 0x0001 #define BIT_STU_RECVFULL 0x0020 -#define CFG_SPI_ENABLE 1 -#define CFG_SPI_DISABLE 0 - -#define CFG_SPI_OUTENABLE 1 -#define CFG_SPI_OUTDISABLE 0 - -#define CFG_SPI_ACTLOW 1 -#define CFG_SPI_ACTHIGH 0 - -#define CFG_SPI_PHASESTART 1 -#define CFG_SPI_PHASEMID 0 - -#define CFG_SPI_MASTER 1 -#define CFG_SPI_SLAVE 0 - -#define CFG_SPI_SENELAST 0 -#define CFG_SPI_SENDZERO 1 - -#define CFG_SPI_RCVFLUSH 1 -#define CFG_SPI_RCVDISCARD 0 - -#define CFG_SPI_LSBFIRST 1 -#define CFG_SPI_MSBFIRST 0 - -#define CFG_SPI_WORDSIZE16 1 -#define CFG_SPI_WORDSIZE8 0 - -#define CFG_SPI_MISOENABLE 1 -#define CFG_SPI_MISODISABLE 0 - -#define CFG_SPI_READ 0x00 -#define CFG_SPI_WRITE 0x01 -#define CFG_SPI_DMAREAD 0x02 -#define CFG_SPI_DMAWRITE 0x03 +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m -#define CFG_SPI_CSCLEARALL 0 -#define CFG_SPI_CHIPSEL1 1 -#define CFG_SPI_CHIPSEL2 2 -#define CFG_SPI_CHIPSEL3 3 -#define CFG_SPI_CHIPSEL4 4 -#define CFG_SPI_CHIPSEL5 5 -#define CFG_SPI_CHIPSEL6 6 -#define CFG_SPI_CHIPSEL7 7 +/* + * bfin spi registers layout + */ +struct bfin_spi_regs { + __BFP(ctl); + __BFP(flg); + __BFP(stat); + __BFP(tdbr); + __BFP(rdbr); + __BFP(baud); + __BFP(shadow); +}; -#define CFG_SPI_CS1VALUE 1 -#define CFG_SPI_CS2VALUE 2 -#define CFG_SPI_CS3VALUE 3 -#define CFG_SPI_CS4VALUE 4 -#define CFG_SPI_CS5VALUE 5 -#define CFG_SPI_CS6VALUE 6 -#define CFG_SPI_CS7VALUE 7 +#undef __BFP -#define CMD_SPI_SET_BAUDRATE 2 -#define CMD_SPI_GET_SYSTEMCLOCK 25 -#define CMD_SPI_SET_WRITECONTINUOUS 26 +#define MAX_CTRL_CS 8 /* cs in spi controller */ /* device.platform_data for SSP controller devices */ struct bfin5xx_spi_master { @@ -120,9 +78,7 @@ struct bfin5xx_spi_chip { u16 ctl_reg; u8 enable_dma; u8 bits_per_word; - u8 cs_change_per_word; u16 cs_chg_udelay; /* Some devices require 16-bit delays */ - u32 cs_gpio; /* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */ u16 idle_tx_val; u8 pio_interrupt; /* Enable spi data irq */ diff --git a/arch/blackfin/include/asm/bfin_can.h b/arch/blackfin/include/asm/bfin_can.h index eec0076a385..b1492e0bcab 100644 --- a/arch/blackfin/include/asm/bfin_can.h +++ b/arch/blackfin/include/asm/bfin_can.h @@ -34,6 +34,7 @@ struct bfin_can_mask_regs { }; struct bfin_can_channel_regs { + /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */ u16 data[8]; __BFP(dlc); __BFP(tsv); @@ -83,16 +84,18 @@ struct bfin_can_regs { __BFP(gif); /* offset 0x9c */ __BFP(control); /* offset 0xa0 */ __BFP(intr); /* offset 0xa4 */ - u32 __pad3[1]; + __BFP(version); /* offset 0xa8 */ __BFP(mbtd); /* offset 0xac */ __BFP(ewr); /* offset 0xb0 */ __BFP(esr); /* offset 0xb4 */ - u32 __pad4[2]; + u32 __pad3[2]; __BFP(ucreg); /* offset 0xc0 */ __BFP(uccnt); /* offset 0xc4 */ __BFP(ucrc); /* offset 0xc8 */ __BFP(uccnf); /* offset 0xcc */ - u32 __pad5[12]; + u32 __pad4[1]; + __BFP(version2); /* offset 0xd4 */ + u32 __pad5[10]; /* * channel(mailbox) mask and message registers diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h new file mode 100644 index 00000000000..3be05faa2c6 --- /dev/null +++ b/arch/blackfin/include/asm/bfin_ppi.h @@ -0,0 +1,53 @@ +/* + * bfin_ppi.h - interface to Blackfin PPIs + * + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_PPI_H__ +#define __ASM_BFIN_PPI_H__ + +#include <linux/types.h> + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin ppi registers layout + */ +struct bfin_ppi_regs { + __BFP(control); + __BFP(status); + __BFP(count); + __BFP(delay); + __BFP(frame); +}; + +/* + * bfin eppi registers layout + */ +struct bfin_eppi_regs { + __BFP(status); + __BFP(hcount); + __BFP(hdelay); + __BFP(vcount); + __BFP(vdelay); + __BFP(frame); + __BFP(line); + __BFP(clkdiv); + u32 control; + u32 fs1w_hbl; + u32 fs1p_avpl; + u32 fs2w_lvb; + u32 fs2p_lavf; + u32 clip; +}; + +#undef __BFP + +#endif diff --git a/arch/blackfin/include/asm/bfin_rotary.h b/arch/blackfin/include/asm/bfin_rotary.h index abdb2af5290..0b6910bdc57 100644 --- a/arch/blackfin/include/asm/bfin_rotary.h +++ b/arch/blackfin/include/asm/bfin_rotary.h @@ -2,7 +2,7 @@ * board initialization should put one of these structures into platform_data * and place the bfin-rotary onto platform_bus named "bfin-rotary". * - * Copyright 2008 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -40,4 +40,76 @@ struct bfin_rotary_platform_data { unsigned short debounce; /* 0..17 */ unsigned short mode; }; + +/* CNT_CONFIG bitmasks */ +#define CNTE (1 << 0) /* Counter Enable */ +#define DEBE (1 << 1) /* Debounce Enable */ +#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */ +#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */ +#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */ +#define CNTMODE_SHIFT 8 +#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */ +#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */ +#define BNDMODE_SHIFT 12 +#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */ +#define INPDIS (1 << 15) /* CUG and CDG Input Disable */ + +#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */ +#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */ +#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */ +#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */ +#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */ + +#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */ +#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */ +#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */ +#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */ + +/* CNT_IMASK bitmasks */ +#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */ +#define UCIE (1 << 1) /* Up count Interrupt Enable */ +#define DCIE (1 << 2) /* Down count Interrupt Enable */ +#define MINCIE (1 << 3) /* Min Count Interrupt Enable */ +#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */ +#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */ +#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */ +#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */ +#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */ +#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */ +#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */ + +/* CNT_STATUS bitmasks */ +#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */ +#define UCII (1 << 1) /* Up count Interrupt Identifier */ +#define DCII (1 << 2) /* Down count Interrupt Identifier */ +#define MINCII (1 << 3) /* Min Count Interrupt Identifier */ +#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */ +#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */ +#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */ +#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */ +#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */ +#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */ +#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */ + +/* CNT_COMMAND bitmasks */ +#define W1LCNT 0xf /* Load Counter Register */ +#define W1LMIN 0xf0 /* Load Min Register */ +#define W1LMAX 0xf00 /* Load Max Register */ +#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */ + +#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */ +#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */ +#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */ + +#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */ +#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */ +#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */ + +#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */ +#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */ +#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */ + +/* CNT_DEBOUNCE bitmasks */ +#define DPRESCALE 0xf /* Load Counter Register */ + #endif diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h index d61d5497c59..6a4cfe2d336 100644 --- a/arch/blackfin/include/asm/bfin_sdh.h +++ b/arch/blackfin/include/asm/bfin_sdh.h @@ -1,7 +1,7 @@ /* - * bfin_sdh.h - Blackfin SDH definitions + * Blackfin Secure Digital Host (SDH) definitions * - * Copyright 2008 Analog Devices Inc. + * Copyright 2008-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -9,6 +9,7 @@ #ifndef __BFIN_SDH_H__ #define __BFIN_SDH_H__ +/* Platform resources */ struct bfin_sd_host { int dma_chan; int irq_int0; @@ -16,4 +17,118 @@ struct bfin_sd_host { u16 pin_req[7]; }; +/* SDH_COMMAND bitmasks */ +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP (1 << 6) /* Response */ +#define CMD_L_RSP (1 << 7) /* Long Response */ +#define CMD_INT_E (1 << 8) /* Command Interrupt */ +#define CMD_PEND_E (1 << 9) /* Command Pending */ +#define CMD_E (1 << 10) /* Command Enable */ + +/* SDH_PWR_CTL bitmasks */ +#define PWR_ON 0x3 /* Power On */ +#define SD_CMD_OD (1 << 6) /* Open Drain Output */ +#define ROD_CTL (1 << 7) /* Rod Control */ + +/* SDH_CLK_CTL bitmasks */ +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E (1 << 9) /* Power Save Enable */ +#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */ +#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */ + +/* SDH_RESP_CMD bitmasks */ +#define RESP_CMD 0x3f /* Response Command */ + +/* SDH_DATA_CTL bitmasks */ +#define DTX_E (1 << 0) /* Data Transfer Enable */ +#define DTX_DIR (1 << 1) /* Data Transfer Direction */ +#define DTX_MODE (1 << 2) /* Data Transfer Mode */ +#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */ + +/* SDH_STATUS bitmasks */ +#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */ +#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */ +#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */ +#define DAT_TIME_OUT (1 << 3) /* Data Time Out */ +#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */ +#define RX_OVERRUN (1 << 5) /* Receive Overrun */ +#define CMD_RESP_END (1 << 6) /* CMD Response End */ +#define CMD_SENT (1 << 7) /* CMD Sent */ +#define DAT_END (1 << 8) /* Data End */ +#define START_BIT_ERR (1 << 9) /* Start Bit Error */ +#define DAT_BLK_END (1 << 10) /* Data Block End */ +#define CMD_ACT (1 << 11) /* CMD Active */ +#define TX_ACT (1 << 12) /* Transmit Active */ +#define RX_ACT (1 << 13) /* Receive Active */ +#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */ +#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */ +#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */ +#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */ +#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */ +#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */ +#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */ +#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */ + +/* SDH_STATUS_CLR bitmasks */ +#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */ +#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */ +#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */ +#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */ +#define DAT_END_STAT (1 << 8) /* Data End Status */ +#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */ +#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */ + +/* SDH_MASK0 bitmasks */ +#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */ +#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */ +#define DAT_END_MASK (1 << 8) /* Data End Mask */ +#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */ +#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */ +#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */ +#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */ + +/* SDH_FIFO_CNT bitmasks */ +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* SDH_E_STATUS bitmasks */ +#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */ +#define SD_CARD_DET (1 << 4) /* SD Card Detect */ + +/* SDH_E_MASK bitmasks */ +#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */ +#define SCD_MSK (1 << 6) /* Mask Card Detect */ + +/* SDH_CFG bitmasks */ +#define CLKS_EN (1 << 0) /* Clocks Enable */ +#define SD4E (1 << 2) /* SDIO 4-Bit Enable */ +#define MWE (1 << 3) /* Moving Window Enable */ +#define SD_RST (1 << 4) /* SDMMC Reset */ +#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */ +#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */ + +/* SDH_RD_WAIT_EN bitmasks */ +#define RWR (1 << 0) /* Read Wait Request */ + #endif diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h index 9626cf7e425..d27600c262c 100644 --- a/arch/blackfin/include/asm/bfin_sport.h +++ b/arch/blackfin/include/asm/bfin_sport.h @@ -115,12 +115,6 @@ struct sport_register { #endif -/* Workaround defBF*.h SPORT MMRs till they get cleansed */ -#undef DTYPE_NORM -#undef SLEN -#undef SP_WOFF -#undef SP_WSIZE - /* SPORT_TCR1 Masks */ #define TSPEN 0x0001 /* TX enable */ #define ITCLK 0x0002 /* Internal TX Clock Select */ diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h new file mode 100644 index 00000000000..e767d649dfc --- /dev/null +++ b/arch/blackfin/include/asm/bfin_twi.h @@ -0,0 +1,45 @@ +/* + * bfin_twi.h - interface to Blackfin TWIs + * + * Copyright 2005-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ASM_BFIN_TWI_H__ +#define __ASM_BFIN_TWI_H__ + +#include <linux/types.h> + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin twi registers layout + */ +struct bfin_twi_regs { + __BFP(clkdiv); + __BFP(control); + __BFP(slave_ctl); + __BFP(slave_stat); + __BFP(slave_addr); + __BFP(master_ctl); + __BFP(master_stat); + __BFP(master_addr); + __BFP(int_stat); + __BFP(int_mask); + __BFP(fifo_ctl); + __BFP(fifo_stat); + u32 __pad[20]; + __BFP(xmt_data8); + __BFP(xmt_data16); + __BFP(rcv_data8); + __BFP(rcv_data16); +}; + +#undef __BFP + +#endif diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h index 605ba8e9b2e..3f7ef4d9779 100644 --- a/arch/blackfin/include/asm/bitops.h +++ b/arch/blackfin/include/asm/bitops.h @@ -22,7 +22,9 @@ #include <asm-generic/bitops/sched.h> #include <asm-generic/bitops/ffs.h> +#include <asm-generic/bitops/const_hweight.h> #include <asm-generic/bitops/lock.h> + #include <asm-generic/bitops/ext2-non-atomic.h> #include <asm-generic/bitops/ext2-atomic.h> #include <asm-generic/bitops/minix.h> @@ -115,29 +117,30 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr) * of bits set) of a N-bit word */ -static inline unsigned int hweight32(unsigned int w) +static inline unsigned int __arch_hweight32(unsigned int w) { unsigned int res; - __asm__ ("%0.l = ONES %0;" + __asm__ ("%0.l = ONES %1;" "%0 = %0.l (Z);" : "=d" (res) : "d" (w)); return res; } -static inline unsigned int hweight64(__u64 w) +static inline unsigned int __arch_hweight64(__u64 w) { - return hweight32((unsigned int)(w >> 32)) + hweight32((unsigned int)w); + return __arch_hweight32((unsigned int)(w >> 32)) + + __arch_hweight32((unsigned int)w); } -static inline unsigned int hweight16(unsigned int w) +static inline unsigned int __arch_hweight16(unsigned int w) { - return hweight32(w & 0xffff); + return __arch_hweight32(w & 0xffff); } -static inline unsigned int hweight8(unsigned int w) +static inline unsigned int __arch_hweight8(unsigned int w) { - return hweight32(w & 0xff); + return __arch_hweight32(w & 0xff); } #endif /* _BLACKFIN_BITOPS_H */ diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index 93f6c634fdf..bd0641a267f 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h @@ -15,7 +15,7 @@ #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define SMP_CACHE_BYTES L1_CACHE_BYTES -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES #ifdef CONFIG_SMP #define __cacheline_aligned diff --git a/arch/blackfin/include/asm/cachectl.h b/arch/blackfin/include/asm/cachectl.h new file mode 100644 index 00000000000..03255df6c1e --- /dev/null +++ b/arch/blackfin/include/asm/cachectl.h @@ -0,0 +1,20 @@ +/* + * based on the mips/cachectl.h + * + * Copyright 2010 Analog Devices Inc. + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL + +/* + * Options for cacheflush system call + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +#endif /* _ASM_CACHECTL */ diff --git a/arch/blackfin/include/asm/cdef_LPBlackfin.h b/arch/blackfin/include/asm/cdef_LPBlackfin.h index 8778e0f0373..59af63c0c2b 100644 --- a/arch/blackfin/include/asm/cdef_LPBlackfin.h +++ b/arch/blackfin/include/asm/cdef_LPBlackfin.h @@ -172,16 +172,19 @@ #define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14,val) #define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) #define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15,val) -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) #define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND,val) #if 0 #define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */ #endif -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) #define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0,val) -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) #define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1,val) +#if !ANOMALY_05000481 +#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) +#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) +#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) +#endif + /* Event/Interrupt Registers*/ #define bfin_read_EVT0() bfin_read32(EVT0) @@ -216,12 +219,16 @@ #define bfin_write_EVT14(val) bfin_write32(EVT14,val) #define bfin_read_EVT15() bfin_read32(EVT15) #define bfin_write_EVT15(val) bfin_write32(EVT15,val) +#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) +#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val) #define bfin_read_IMASK() bfin_read32(IMASK) #define bfin_write_IMASK(val) bfin_write32(IMASK,val) #define bfin_read_IPEND() bfin_read32(IPEND) #define bfin_write_IPEND(val) bfin_write32(IPEND,val) #define bfin_read_ILAT() bfin_read32(ILAT) #define bfin_write_ILAT(val) bfin_write32(ILAT,val) +#define bfin_read_IPRIO() bfin_read32(IPRIO) +#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val) /*Core Timer Registers*/ #define bfin_read_TCNTL() bfin_read32(TCNTL) @@ -299,8 +306,4 @@ #define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) #define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val) -/* -#define IPRIO 0xFFE02110 -*/ - #endif /* _CDEF_LPBLACKFIN_H */ diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h index f342ff0319d..e3f0f4c4981 100644 --- a/arch/blackfin/include/asm/def_LPBlackfin.h +++ b/arch/blackfin/include/asm/def_LPBlackfin.h @@ -50,6 +50,23 @@ #define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) #define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) +#define bfin_read(addr) \ +({ \ + sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ + sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ + sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ + ({ BUG(); 0; }); \ +}) +#define bfin_write(addr, val) \ +({ \ + switch (sizeof(*(addr))) { \ + case 1: bfin_write8(addr, val); break; \ + case 2: bfin_write16(addr, val); break; \ + case 4: bfin_write32(addr, val); break; \ + default: BUG(); \ + } \ +}) + #endif /* __ASSEMBLY__ */ /************************************************** @@ -377,6 +394,7 @@ #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ +#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */ #define IMASK 0xFFE02104 /* Interrupt Mask Register */ #define IPEND 0xFFE02108 /* Interrupt Pending Register */ #define ILAT 0xFFE0210C /* Interrupt Latch Register */ diff --git a/arch/blackfin/include/asm/dma-mapping.h b/arch/blackfin/include/asm/dma-mapping.h index 212cb80fd74..bbf461076a0 100644 --- a/arch/blackfin/include/asm/dma-mapping.h +++ b/arch/blackfin/include/asm/dma-mapping.h @@ -21,8 +21,6 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) #define dma_supported(d, m) (1) -#define dma_get_cache_alignment() (32) -#define dma_is_consistent(d, h) (1) static inline int dma_set_mask(struct device *dev, u64 dma_mask) diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h index 2c09b1d50ec..eedf3ca65ba 100644 --- a/arch/blackfin/include/asm/dma.h +++ b/arch/blackfin/include/asm/dma.h @@ -276,6 +276,7 @@ static inline void clear_dma_irqstat(unsigned int channel) } void *dma_memcpy(void *dest, const void *src, size_t count); +void *dma_memcpy_nocache(void *dest, const void *src, size_t count); void *safe_dma_memcpy(void *dest, const void *src, size_t count); void blackfin_dma_early_init(void); void early_dma_memcpy(void *dest, const void *src, size_t count); diff --git a/arch/blackfin/include/asm/elf.h b/arch/blackfin/include/asm/elf.h index 117713adea7..e6c6812a9ab 100644 --- a/arch/blackfin/include/asm/elf.h +++ b/arch/blackfin/include/asm/elf.h @@ -119,6 +119,7 @@ do { \ #define ELF_CORE_COPY_REGS(pr_reg, regs) \ memcpy((char *) &pr_reg, (char *)regs, \ sizeof(struct pt_regs)); +#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */ /* This yields a mask that user programs can use to figure out what instruction set this cpu supports. */ diff --git a/arch/blackfin/include/asm/entry.h b/arch/blackfin/include/asm/entry.h index a6886f6e481..4104d5783e2 100644 --- a/arch/blackfin/include/asm/entry.h +++ b/arch/blackfin/include/asm/entry.h @@ -15,14 +15,6 @@ #define LFLUSH_I_AND_D 0x00000808 #define LSIGTRAP 5 -/* process bits for task_struct.flags */ -#define PF_TRACESYS_OFF 3 -#define PF_TRACESYS_BIT 5 -#define PF_PTRACED_OFF 3 -#define PF_PTRACED_BIT 4 -#define PF_DTRACE_OFF 1 -#define PF_DTRACE_BIT 5 - /* * NOTE! The single-stepping code assumes that all interrupt handlers * start by saving SYSCFG on the stack with their first instruction. diff --git a/arch/blackfin/include/asm/ftrace.h b/arch/blackfin/include/asm/ftrace.h index 4cfe2d9ba7e..8a029505d7b 100644 --- a/arch/blackfin/include/asm/ftrace.h +++ b/arch/blackfin/include/asm/ftrace.h @@ -12,6 +12,22 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_DYNAMIC_FTRACE + +extern void _mcount(void); +#define MCOUNT_ADDR ((unsigned long)_mcount) + +static inline unsigned long ftrace_call_adjust(unsigned long addr) +{ + return addr; +} + +struct dyn_arch_ftrace { + /* No extra data needed for Blackfin */ +}; + +#endif + #ifdef CONFIG_FRAME_POINTER #include <linux/mm.h> diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 01b19d0cf50..1ef8417f5d2 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -7,63 +7,63 @@ #ifndef __ARCH_BLACKFIN_GPIO_H__ #define __ARCH_BLACKFIN_GPIO_H__ -#define gpio_bank(x) ((x) >> 4) -#define gpio_bit(x) (1<<((x) & 0xF)) -#define gpio_sub_n(x) ((x) & 0xF) +#define gpio_bank(x) ((x) >> 4) +#define gpio_bit(x) (1<<((x) & 0xF)) +#define gpio_sub_n(x) ((x) & 0xF) -#define GPIO_BANKSIZE 16 -#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE) +#define GPIO_BANKSIZE 16 +#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE) #include <mach/gpio.h> -#define GPIO_0 0 -#define GPIO_1 1 -#define GPIO_2 2 -#define GPIO_3 3 -#define GPIO_4 4 -#define GPIO_5 5 -#define GPIO_6 6 -#define GPIO_7 7 -#define GPIO_8 8 -#define GPIO_9 9 -#define GPIO_10 10 -#define GPIO_11 11 -#define GPIO_12 12 -#define GPIO_13 13 -#define GPIO_14 14 -#define GPIO_15 15 -#define GPIO_16 16 -#define GPIO_17 17 -#define GPIO_18 18 -#define GPIO_19 19 -#define GPIO_20 20 -#define GPIO_21 21 -#define GPIO_22 22 -#define GPIO_23 23 -#define GPIO_24 24 -#define GPIO_25 25 -#define GPIO_26 26 -#define GPIO_27 27 -#define GPIO_28 28 -#define GPIO_29 29 -#define GPIO_30 30 -#define GPIO_31 31 -#define GPIO_32 32 -#define GPIO_33 33 -#define GPIO_34 34 -#define GPIO_35 35 -#define GPIO_36 36 -#define GPIO_37 37 -#define GPIO_38 38 -#define GPIO_39 39 -#define GPIO_40 40 -#define GPIO_41 41 -#define GPIO_42 42 -#define GPIO_43 43 -#define GPIO_44 44 -#define GPIO_45 45 -#define GPIO_46 46 -#define GPIO_47 47 +#define GPIO_0 0 +#define GPIO_1 1 +#define GPIO_2 2 +#define GPIO_3 3 +#define GPIO_4 4 +#define GPIO_5 5 +#define GPIO_6 6 +#define GPIO_7 7 +#define GPIO_8 8 +#define GPIO_9 9 +#define GPIO_10 10 +#define GPIO_11 11 +#define GPIO_12 12 +#define GPIO_13 13 +#define GPIO_14 14 +#define GPIO_15 15 +#define GPIO_16 16 +#define GPIO_17 17 +#define GPIO_18 18 +#define GPIO_19 19 +#define GPIO_20 20 +#define GPIO_21 21 +#define GPIO_22 22 +#define GPIO_23 23 +#define GPIO_24 24 +#define GPIO_25 25 +#define GPIO_26 26 +#define GPIO_27 27 +#define GPIO_28 28 +#define GPIO_29 29 +#define GPIO_30 30 +#define GPIO_31 31 +#define GPIO_32 32 +#define GPIO_33 33 +#define GPIO_34 34 +#define GPIO_35 35 +#define GPIO_36 36 +#define GPIO_37 37 +#define GPIO_38 38 +#define GPIO_39 39 +#define GPIO_40 40 +#define GPIO_41 41 +#define GPIO_42 42 +#define GPIO_43 43 +#define GPIO_44 44 +#define GPIO_45 45 +#define GPIO_46 46 +#define GPIO_47 47 #define PERIPHERAL_USAGE 1 #define GPIO_USAGE 0 @@ -279,6 +279,11 @@ static inline int gpio_direction_output(unsigned gpio, int value) return bfin_gpio_direction_output(gpio, value); } +static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) +{ + return -EINVAL; +} + static inline int gpio_get_value(unsigned gpio) { return bfin_gpio_get_value(gpio); diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h index 29e55b9d88b..234fbac17ec 100644 --- a/arch/blackfin/include/asm/io.h +++ b/arch/blackfin/include/asm/io.h @@ -124,7 +124,13 @@ static inline unsigned int readl(const volatile void __iomem *addr) #define iowrite16(val, x) writew(val, x) #define iowrite32(val, x) writel(val, x) -#define mmiowb() wmb() +/** + * I/O write barrier + * + * Ensure ordering of I/O space writes. This will make sure that writes + * following the barrier will arrive after all previous writes. + */ +#define mmiowb() do { SSYNC(); wmb(); } while (0) #define IO_SPACE_LIMIT 0xffffffff diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h index d3b40449ca0..40f94a704c0 100644 --- a/arch/blackfin/include/asm/ipipe.h +++ b/arch/blackfin/include/asm/ipipe.h @@ -49,7 +49,7 @@ #define prepare_arch_switch(next) \ do { \ ipipe_schedule_notify(current, next); \ - local_irq_disable_hw(); \ + hard_local_irq_disable(); \ } while (0) #define task_hijacked(p) \ @@ -57,7 +57,7 @@ do { \ int __x__ = __ipipe_root_domain_p; \ __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \ if (__x__) \ - local_irq_enable_hw(); \ + hard_local_irq_enable(); \ !__x__; \ }) @@ -167,7 +167,7 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul) #define __ipipe_run_isr(ipd, irq) \ do { \ if (!__ipipe_pipeline_head_p(ipd)) \ - local_irq_enable_hw(); \ + hard_local_irq_enable(); \ if (ipd == ipipe_root_domain) { \ if (unlikely(ipipe_virtual_irq_p(irq))) { \ irq_enter(); \ @@ -183,7 +183,7 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul) __ipipe_run_irqtail(); \ __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ } \ - local_irq_disable_hw(); \ + hard_local_irq_disable(); \ } while (0) #define __ipipe_syscall_watched_p(p, sc) \ diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h index 813a1af3e86..41c4d70544e 100644 --- a/arch/blackfin/include/asm/irqflags.h +++ b/arch/blackfin/include/asm/irqflags.h @@ -8,6 +8,8 @@ #ifndef __ASM_BFIN_IRQFLAGS_H__ #define __ASM_BFIN_IRQFLAGS_H__ +#include <mach/blackfin.h> + #ifdef CONFIG_SMP # include <asm/pda.h> # include <asm/processor.h> @@ -31,54 +33,108 @@ static inline unsigned long bfin_cli(void) return flags; } -#ifdef CONFIG_IPIPE - -#include <linux/compiler.h> -#include <linux/ipipe_base.h> -#include <linux/ipipe_trace.h> - #ifdef CONFIG_DEBUG_HWERR # define bfin_no_irqs 0x3f #else # define bfin_no_irqs 0x1f #endif -#define raw_local_irq_disable() \ - do { \ - ipipe_check_context(ipipe_root_domain); \ - __ipipe_stall_root(); \ - barrier(); \ - } while (0) +/*****************************************************************************/ +/* + * Hard, untraced CPU interrupt flag manipulation and access. + */ +static inline void __hard_local_irq_disable(void) +{ + bfin_cli(); +} + +static inline void __hard_local_irq_enable(void) +{ + bfin_sti(bfin_irq_flags); +} + +static inline unsigned long hard_local_save_flags(void) +{ + return bfin_read_IMASK(); +} -#define raw_local_irq_enable() \ - do { \ - barrier(); \ - ipipe_check_context(ipipe_root_domain); \ - __ipipe_unstall_root(); \ - } while (0) +static inline unsigned long __hard_local_irq_save(void) +{ + unsigned long flags; + flags = bfin_cli(); +#ifdef CONFIG_DEBUG_HWERR + bfin_sti(0x3f); +#endif + return flags; +} + +static inline int hard_irqs_disabled_flags(unsigned long flags) +{ + return (flags & ~0x3f) == 0; +} + +static inline int hard_irqs_disabled(void) +{ + unsigned long flags = hard_local_save_flags(); + return hard_irqs_disabled_flags(flags); +} + +static inline void __hard_local_irq_restore(unsigned long flags) +{ + if (!hard_irqs_disabled_flags(flags)) + __hard_local_irq_enable(); +} + +/*****************************************************************************/ +/* + * Interrupt pipe handling. + */ +#ifdef CONFIG_IPIPE + +#include <linux/compiler.h> +#include <linux/ipipe_base.h> +#include <linux/ipipe_trace.h> + +/* + * Interrupt pipe interface to linux/irqflags.h. + */ +static inline void arch_local_irq_disable(void) +{ + ipipe_check_context(ipipe_root_domain); + __ipipe_stall_root(); + barrier(); +} -#define raw_local_save_flags_ptr(x) \ - do { \ - *(x) = __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; \ - } while (0) +static inline void arch_local_irq_enable(void) +{ + barrier(); + ipipe_check_context(ipipe_root_domain); + __ipipe_unstall_root(); +} -#define raw_local_save_flags(x) raw_local_save_flags_ptr(&(x)) +static inline unsigned long arch_local_save_flags(void) +{ + return __ipipe_test_root() ? bfin_no_irqs : bfin_irq_flags; +} -#define raw_irqs_disabled_flags(x) ((x) == bfin_no_irqs) +static inline int arch_irqs_disabled_flags(unsigned long flags) +{ + return flags == bfin_no_irqs; +} -#define raw_local_irq_save_ptr(x) \ - do { \ - *(x) = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; \ - barrier(); \ - } while (0) +static inline void arch_local_irq_save_ptr(unsigned long *_flags) +{ + x = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; + barrier(); +} -#define raw_local_irq_save(x) \ - do { \ - ipipe_check_context(ipipe_root_domain); \ - raw_local_irq_save_ptr(&(x)); \ - } while (0) +static inline unsigned long arch_local_irq_save(void) +{ + ipipe_check_context(ipipe_root_domain); + return __hard_local_irq_save(); +} -static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real) +static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real) { /* * Merge virtual and real interrupt mask bits into a single @@ -87,130 +143,79 @@ static inline unsigned long raw_mangle_irq_bits(int virt, unsigned long real) return (real & ~(1 << 31)) | ((virt != 0) << 31); } -static inline int raw_demangle_irq_bits(unsigned long *x) +static inline int arch_demangle_irq_bits(unsigned long *x) { int virt = (*x & (1 << 31)) != 0; *x &= ~(1L << 31); return virt; } -static inline void local_irq_disable_hw_notrace(void) +/* + * Interface to various arch routines that may be traced. + */ +#ifdef CONFIG_IPIPE_TRACE_IRQSOFF +static inline void hard_local_irq_disable(void) { - bfin_cli(); + if (!hard_irqs_disabled()) { + __hard_local_irq_disable(); + ipipe_trace_begin(0x80000000); + } } -static inline void local_irq_enable_hw_notrace(void) +static inline void hard_local_irq_enable(void) { - bfin_sti(bfin_irq_flags); + if (hard_irqs_disabled()) { + ipipe_trace_end(0x80000000); + __hard_local_irq_enable(); + } } -#define local_save_flags_hw(flags) \ - do { \ - (flags) = bfin_read_IMASK(); \ - } while (0) - -#define irqs_disabled_flags_hw(flags) (((flags) & ~0x3f) == 0) - -#define irqs_disabled_hw() \ - ({ \ - unsigned long flags; \ - local_save_flags_hw(flags); \ - irqs_disabled_flags_hw(flags); \ - }) - -static inline void local_irq_save_ptr_hw(unsigned long *flags) +static inline unsigned long hard_local_irq_save(void) { - *flags = bfin_cli(); -#ifdef CONFIG_DEBUG_HWERR - bfin_sti(0x3f); -#endif + unsigned long flags = hard_local_save_flags(); + if (!hard_irqs_disabled_flags(flags)) { + __hard_local_irq_disable(); + ipipe_trace_begin(0x80000001); + } + return flags; } -#define local_irq_save_hw_notrace(flags) \ - do { \ - local_irq_save_ptr_hw(&(flags)); \ - } while (0) - -static inline void local_irq_restore_hw_notrace(unsigned long flags) +static inline void hard_local_irq_restore(unsigned long flags) { - if (!irqs_disabled_flags_hw(flags)) - local_irq_enable_hw_notrace(); + if (!hard_irqs_disabled_flags(flags)) { + ipipe_trace_end(0x80000001); + __hard_local_irq_enable(); + } } -#ifdef CONFIG_IPIPE_TRACE_IRQSOFF -# define local_irq_disable_hw() \ - do { \ - if (!irqs_disabled_hw()) { \ - local_irq_disable_hw_notrace(); \ - ipipe_trace_begin(0x80000000); \ - } \ - } while (0) -# define local_irq_enable_hw() \ - do { \ - if (irqs_disabled_hw()) { \ - ipipe_trace_end(0x80000000); \ - local_irq_enable_hw_notrace(); \ - } \ - } while (0) -# define local_irq_save_hw(flags) \ - do { \ - local_save_flags_hw(flags); \ - if (!irqs_disabled_flags_hw(flags)) { \ - local_irq_disable_hw_notrace(); \ - ipipe_trace_begin(0x80000001); \ - } \ - } while (0) -# define local_irq_restore_hw(flags) \ - do { \ - if (!irqs_disabled_flags_hw(flags)) { \ - ipipe_trace_end(0x80000001); \ - local_irq_enable_hw_notrace(); \ - } \ - } while (0) #else /* !CONFIG_IPIPE_TRACE_IRQSOFF */ -# define local_irq_disable_hw() local_irq_disable_hw_notrace() -# define local_irq_enable_hw() local_irq_enable_hw_notrace() -# define local_irq_save_hw(flags) local_irq_save_hw_notrace(flags) -# define local_irq_restore_hw(flags) local_irq_restore_hw_notrace(flags) +# define hard_local_irq_disable() __hard_local_irq_disable() +# define hard_local_irq_enable() __hard_local_irq_enable() +# define hard_local_irq_save() __hard_local_irq_save() +# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) #endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */ #else /* CONFIG_IPIPE */ -static inline void raw_local_irq_disable(void) -{ - bfin_cli(); -} -static inline void raw_local_irq_enable(void) -{ - bfin_sti(bfin_irq_flags); -} - -#define raw_local_save_flags(flags) do { (flags) = bfin_read_IMASK(); } while (0) - -#define raw_irqs_disabled_flags(flags) (((flags) & ~0x3f) == 0) +/* + * Direct interface to linux/irqflags.h. + */ +#define arch_local_save_flags() hard_local_save_flags() +#define arch_local_irq_save(flags) __hard_local_irq_save() +#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags) +#define arch_local_irq_enable() __hard_local_irq_enable() +#define arch_local_irq_disable() __hard_local_irq_disable() +#define arch_irqs_disabled_flags(flags) hard_irqs_disabled_flags(flags) +#define arch_irqs_disabled() hard_irqs_disabled() -static inline unsigned long __raw_local_irq_save(void) -{ - unsigned long flags = bfin_cli(); -#ifdef CONFIG_DEBUG_HWERR - bfin_sti(0x3f); -#endif - return flags; -} -#define raw_local_irq_save(flags) do { (flags) = __raw_local_irq_save(); } while (0) +/* + * Interface to various arch routines that may be traced. + */ +#define hard_local_irq_save() __hard_local_irq_save() +#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) +#define hard_local_irq_enable() __hard_local_irq_enable() +#define hard_local_irq_disable() __hard_local_irq_disable() -#define local_irq_save_hw(flags) raw_local_irq_save(flags) -#define local_irq_restore_hw(flags) raw_local_irq_restore(flags) -#define local_irq_enable_hw() raw_local_irq_enable() -#define local_irq_disable_hw() raw_local_irq_disable() -#define irqs_disabled_hw() irqs_disabled() #endif /* !CONFIG_IPIPE */ - -static inline void raw_local_irq_restore(unsigned long flags) -{ - if (!raw_irqs_disabled_flags(flags)) - raw_local_irq_enable(); -} - #endif diff --git a/arch/blackfin/include/asm/local64.h b/arch/blackfin/include/asm/local64.h new file mode 100644 index 00000000000..36c93b5cc23 --- /dev/null +++ b/arch/blackfin/include/asm/local64.h @@ -0,0 +1 @@ +#include <asm-generic/local64.h> diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index 7c8fe834ff2..237579935e2 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h @@ -10,7 +10,6 @@ #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \ - defined(CONFIG_MEM_GENERIC_BOARD) || \ defined(CONFIG_MEM_MT48LC32M8A2_75) || \ defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \ defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ @@ -178,7 +177,6 @@ #if defined(CONFIG_MEM_MT48LC32M8A2_75) || \ defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ - defined(CONFIG_MEM_GENERIC_BOARD) || \ defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \ defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ defined(CONFIG_MEM_MT48LC32M8A2_75) @@ -248,22 +246,6 @@ #define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15)) #endif -#if defined(CONFIG_MEM_GENERIC_BOARD) -#define DDR_SIZE DEVSZ_512 -#define DDR_WIDTH DEVWD_16 -#define DDR_MAX_tCK 13 - -#define DDR_tRCD DDR_TRCD(3) -#define DDR_tWTR DDR_TWTR(2) -#define DDR_tWR DDR_TWR(2) -#define DDR_tMRD DDR_TMRD(2) -#define DDR_tRP DDR_TRP(3) -#define DDR_tRAS DDR_TRAS(7) -#define DDR_tRC DDR_TRC(10) -#define DDR_tRFC DDR_TRFC(12) -#define DDR_tREFI DDR_TREFI(1288) -#endif - #if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK)) # error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)." #elif(CONFIG_SCLK_HZ <= 133333333) diff --git a/arch/blackfin/include/asm/mmu_context.h b/arch/blackfin/include/asm/mmu_context.h index e1a9b4624f9..3828c70e7a2 100644 --- a/arch/blackfin/include/asm/mmu_context.h +++ b/arch/blackfin/include/asm/mmu_context.h @@ -97,8 +97,8 @@ static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next } #ifdef CONFIG_IPIPE -#define lock_mm_switch(flags) local_irq_save_hw_cond(flags) -#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags) +#define lock_mm_switch(flags) flags = hard_local_irq_save_cond() +#define unlock_mm_switch(flags) hard_local_irq_restore_cond(flags) #else #define lock_mm_switch(flags) do { (void)(flags); } while (0) #define unlock_mm_switch(flags) do { (void)(flags); } while (0) @@ -205,9 +205,9 @@ static inline void destroy_context(struct mm_struct *mm) } #define ipipe_mm_switch_protect(flags) \ - local_irq_save_hw_cond(flags) + flags = hard_local_irq_save_cond() #define ipipe_mm_switch_unprotect(flags) \ - local_irq_restore_hw_cond(flags) + hard_local_irq_restore_cond(flags) #endif diff --git a/arch/blackfin/include/asm/nand.h b/arch/blackfin/include/asm/nand.h index 3a1e79dfc8d..256c50d8d46 100644 --- a/arch/blackfin/include/asm/nand.h +++ b/arch/blackfin/include/asm/nand.h @@ -15,8 +15,6 @@ * partitions = mtd partition list */ -#define NFC_PG_SIZE_256 0 -#define NFC_PG_SIZE_512 1 #define NFC_PG_SIZE_OFFSET 9 #define NFC_NWIDTH_8 0 @@ -30,7 +28,6 @@ struct bf5xx_nand_platform { /* NAND chip information */ - unsigned short page_size; unsigned short data_width; /* RD/WR strobe delay timing information, all times in SCLK cycles */ diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h index edd8ef3a378..9b1e2c37b32 100644 --- a/arch/blackfin/include/asm/portmux.h +++ b/arch/blackfin/include/asm/portmux.h @@ -1,9 +1,9 @@ /* * Common header file for Blackfin family of processors * - * Copyright 2007-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. + * Copyright 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. */ #ifndef _PORTMUX_H_ @@ -1042,8 +1042,8 @@ void peripheral_free_list(const unsigned short per[]); #define P_NOR_CLK P_UNDEF #endif -#ifndef P_TMRCLK -#define P_TMRCLK P_UNDEF +#ifndef P_TMRCLK +#define P_TMRCLK P_UNDEF #endif #ifndef P_AMC_ARDY_NOR_WAIT diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h index aaa1c6c2bc1..832d7c009a2 100644 --- a/arch/blackfin/include/asm/ptrace.h +++ b/arch/blackfin/include/asm/ptrace.h @@ -113,6 +113,9 @@ extern void user_disable_single_step(struct task_struct *child); /* common code demands this function */ #define ptrace_disable(child) user_disable_single_step(child) +extern int is_user_addr_valid(struct task_struct *child, + unsigned long start, unsigned long len); + /* * Get the address of the live pt_regs for the specified task. * These are saved onto the top kernel stack when the process diff --git a/arch/blackfin/include/asm/scatterlist.h b/arch/blackfin/include/asm/scatterlist.h index 64d41d34ab0..d177a158895 100644 --- a/arch/blackfin/include/asm/scatterlist.h +++ b/arch/blackfin/include/asm/scatterlist.h @@ -3,6 +3,4 @@ #include <asm-generic/scatterlist.h> -#define ISA_DMA_THRESHOLD (0xffffffff) - #endif /* !(_BLACKFIN_SCATTERLIST_H) */ diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h index 94a4a12e3bf..a0cb0caff15 100644 --- a/arch/blackfin/include/asm/serial.h +++ b/arch/blackfin/include/asm/serial.h @@ -1,2 +1 @@ #include <asm-generic/serial.h> -#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH diff --git a/arch/blackfin/include/asm/system.h b/arch/blackfin/include/asm/system.h index dde19b1d25f..19e2c7c3e63 100644 --- a/arch/blackfin/include/asm/system.h +++ b/arch/blackfin/include/asm/system.h @@ -117,7 +117,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, unsigned long tmp = 0; unsigned long flags; - local_irq_save_hw(flags); + flags = hard_local_irq_save(); switch (size) { case 1: @@ -139,7 +139,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); break; } - local_irq_restore_hw(flags); + hard_local_irq_restore(flags); return tmp; } diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index 22886cbdae7..928ae975b87 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -389,8 +389,12 @@ #define __NR_rt_tgsigqueueinfo 368 #define __NR_perf_event_open 369 #define __NR_recvmmsg 370 +#define __NR_fanotify_init 371 +#define __NR_fanotify_mark 372 +#define __NR_prlimit64 373 +#define __NR_cacheflush 374 -#define __NR_syscall 371 +#define __NR_syscall 375 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ |