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authorMichal Marek <mmarek@suse.cz>2010-12-14 22:01:55 +0100
committerMichal Marek <mmarek@suse.cz>2010-12-14 22:01:55 +0100
commit8990c1bc4be46473ad19bf2fa612ca57286f3df4 (patch)
tree3cea60576903a1d26c67e6ec62891b524d390e95 /arch/blackfin/include/asm/bfin_ppi.h
parent2979076fbf17a0947d6eba367b0cac19c907c160 (diff)
parentc8ddb2713c624f432fa5fe3c7ecffcdda46ea0d4 (diff)
Merge commit 'v2.6.37-rc1' into kbuild/kbuild
Diffstat (limited to 'arch/blackfin/include/asm/bfin_ppi.h')
-rw-r--r--arch/blackfin/include/asm/bfin_ppi.h53
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h
new file mode 100644
index 00000000000..3be05faa2c6
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_ppi.h
@@ -0,0 +1,53 @@
+/*
+ * bfin_ppi.h - interface to Blackfin PPIs
+ *
+ * Copyright 2005-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BFIN_PPI_H__
+#define __ASM_BFIN_PPI_H__
+
+#include <linux/types.h>
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits. So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+
+/*
+ * bfin ppi registers layout
+ */
+struct bfin_ppi_regs {
+ __BFP(control);
+ __BFP(status);
+ __BFP(count);
+ __BFP(delay);
+ __BFP(frame);
+};
+
+/*
+ * bfin eppi registers layout
+ */
+struct bfin_eppi_regs {
+ __BFP(status);
+ __BFP(hcount);
+ __BFP(hdelay);
+ __BFP(vcount);
+ __BFP(vdelay);
+ __BFP(frame);
+ __BFP(line);
+ __BFP(clkdiv);
+ u32 control;
+ u32 fs1w_hbl;
+ u32 fs1p_avpl;
+ u32 fs2w_lvb;
+ u32 fs2p_lavf;
+ u32 clip;
+};
+
+#undef __BFP
+
+#endif