diff options
| author | Abhilash Kesavan <a.kesavan@samsung.com> | 2010-06-08 16:55:45 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-08-05 18:32:50 +0900 |
| commit | 0ab0b6d226caa4a0268ecbce76a7376c3f40ee6b (patch) | |
| tree | 729f66aa696b663b92e04d606eb1686b0f353307 /arch/arm/mach-s3c64xx/include/mach | |
| parent | db90005b5bdb7195b55e295548d7a7eb2014d94c (diff) | |
ARM: S3C64XX: Add support for Compact Flash driver on SMDK6410
Following is added for the CF-ATA driver:
- Platform data strucure instantiation
- Platform device enabling code
- Addition of cfcon clock
- Platform-specific gpio setup code
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach')
| -rw-r--r-- | arch/arm/mach-s3c64xx/include/mach/map.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 5 |
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h index e1eab3c94ae..1caaa5f25f8 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c64xx/include/mach/map.h @@ -86,6 +86,9 @@ #define S3C64XX_SZ_GPIO SZ_4K #define S3C64XX_PA_SDRAM (0x50000000) + +#define S3C64XX_PA_CFCON (0x70300000) + #define S3C64XX_PA_VIC0 (0x71200000) #define S3C64XX_PA_VIC1 (0x71300000) @@ -120,5 +123,6 @@ #define S3C_PA_WDT S3C64XX_PA_WATCHDOG #define SAMSUNG_PA_ADC S3C64XX_PA_ADC +#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON #endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 0114eb0c1fe..05332b998ec 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h @@ -34,6 +34,7 @@ #define S3C_SCLK_GATE S3C_CLKREG(0x38) #define S3C_MEM0_GATE S3C_CLKREG(0x3C) #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) +#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120) /* CLKDIV0 */ #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) @@ -154,4 +155,8 @@ #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) #define S3C6400_CLKSRC_MFC (1 << 4) +/* MEM_SYS_CFG */ +#define MEM_SYS_CFG_INDEP_CF 0x4000 +#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 + #endif /* _PLAT_REGS_CLOCK_H */ |