diff options
| author | Saeed Bishara <saeed@marvell.com> | 2010-06-08 14:21:34 +0300 |
|---|---|---|
| committer | Nicolas Pitre <nico@fluxnic.net> | 2010-07-16 22:01:59 -0400 |
| commit | ffd58bd2e45168de21d257d26ee32843b286d3b3 (patch) | |
| tree | 6015a09c82add039c532a6cc41502c5eae31ccd4 /arch/arm/mach-kirkwood/addr-map.c | |
| parent | 35fe2fc44ac4202261317ccce2ef69991bc01c57 (diff) | |
[ARM] Kirkwood: add support for PCIe1
This patch extends the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Diffstat (limited to 'arch/arm/mach-kirkwood/addr-map.c')
| -rw-r--r-- | arch/arm/mach-kirkwood/addr-map.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c index 2e69168fc69..8d03bcef518 100644 --- a/arch/arm/mach-kirkwood/addr-map.c +++ b/arch/arm/mach-kirkwood/addr-map.c @@ -31,6 +31,8 @@ #define ATTR_DEV_CS0 0x3e #define ATTR_PCIE_IO 0xe0 #define ATTR_PCIE_MEM 0xe8 +#define ATTR_PCIE1_IO 0xd0 +#define ATTR_PCIE1_MEM 0xd8 #define ATTR_SRAM 0x01 /* @@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void) TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); + setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE, + TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE); + setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE, + TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE); /* * Setup window for NAND controller. */ - setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, + setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, TARGET_DEV_BUS, ATTR_DEV_NAND, -1); /* * Setup window for SRAM. */ - setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, + setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1); /* |