|author||SAN People <firstname.lastname@example.org>||2006-01-09 17:05:41 +0000|
|committer||Russell King <email@example.com>||2006-01-09 17:05:41 +0000|
[ARM] 3240/2: AT91RM9200 support for 2.6 (Core)
Patch from SAN People Following changes were made to clock.c: 1) Replaced <asm/hardware/clock.h> with <linux/clk.h> 2) Removed old unused clk_enable & clk_disable. 3) Replaced clk_use/clk_unuse with clk_enable/clk_disable. Otherwise it's the same as the previous patch. Signed-off-by: Andrew Victor <firstname.lastname@example.org> Signed-off-by: Russell King <email@example.com>
Diffstat (limited to 'include/asm-arm/arch-at91rm9200/system.h')
1 files changed, 51 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91rm9200/system.h b/include/asm-arm/arch-at91rm9200/system.h
new file mode 100644
@@ -0,0 +1,51 @@
+ * include/asm-arm/arch-at91rm9200/system.h
+ * Copyright (C) 2003 SAN People
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+static inline void arch_idle(void)
+ * Disable the processor clock. The processor will be automatically
+ * re-enabled by an interrupt or by a reset.
+// at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+ * Set the processor (CP15) into 'Wait for Interrupt' mode.
+ * Unlike disabling the processor clock via the PMC (above)
+ * this allows the processor to be woken via JTAG.
+static inline void arch_reset(char mode)
+ * Perform a hardware reset with the use of the Watchdog timer.
+ at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+ at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);