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authorPeter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>2009-02-01 01:18:58 -0800
committerDavid S. Miller <davem@davemloft.net>2009-02-01 01:18:58 -0800
commiteb7f139ce523bfe03b1628c66d3e1d50f3c07196 (patch)
treed41b641e1a94911aaddc22b63d3d470f6cfd3ef1 /drivers/net/ixgbe/ixgbe_type.h
parent2f21bdd3542838dc5513a585a32aa13f01b019e7 (diff)
ixgbe: Refactor MSI-X allocation mechanism
Our current MSI-X allocation mechanism does not support new hardware at all. It also isn't getting the actual number of supported MSI-X vectors from the device. This patch allows the number of MSI-X vectors to be specific to a device, plus it gets the number of MSI-X vectors available from PCIe configuration space. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_type.h')
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 883ff821153..0d1d1d20aff 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -821,6 +821,10 @@
#define IXGBE_FW_PTR 0x0F
#define IXGBE_PBANUM0_PTR 0x15
#define IXGBE_PBANUM1_PTR 0x16
+#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
+
+/* MSI-X capability fields masks */
+#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
/* Legacy EEPROM word offsets */
#define IXGBE_ISCSI_BOOT_CAPS 0x0033
@@ -1451,6 +1455,7 @@ struct ixgbe_mac_info {
u32 num_rar_entries;
u32 max_tx_queues;
u32 max_rx_queues;
+ u32 max_msix_vectors;
u32 link_attach_type;
u32 link_mode_select;
bool link_settings_loaded;