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| author | David S. Miller <davem@davemloft.net> | 2009-08-12 17:44:53 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-08-12 17:44:53 -0700 |
| commit | aa11d958d1a6572eda08214d7c6a735804fe48a5 (patch) | |
| tree | d025b05270ad1e010660d17eeadc6ac3c1abbd7d /drivers/net/ixgbe/ixgbe_type.h | |
| parent | 07f6642ee9418e962e54cbc07471cfe2e559c568 (diff) | |
| parent | 9799218ae36910af50f002a5db1802d576fffb43 (diff) | |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts:
arch/microblaze/include/asm/socket.h
Diffstat (limited to 'drivers/net/ixgbe/ixgbe_type.h')
| -rw-r--r-- | drivers/net/ixgbe/ixgbe_type.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h index 17ee3890a0a..f0f3406ef00 100644 --- a/drivers/net/ixgbe/ixgbe_type.h +++ b/drivers/net/ixgbe/ixgbe_type.h @@ -719,6 +719,12 @@ #define IXGBE_ECC_STATUS_82599 0x110E0 #define IXGBE_BAR_CTRL_82599 0x110F4 +/* PCI Express Control */ +#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 +#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 +#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 +#define IXGBE_GCR_CAP_VER2 0x00040000 + /* Time Sync Registers */ #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ @@ -1522,6 +1528,7 @@ /* PCI Bus Info */ #define IXGBE_PCI_LINK_STATUS 0xB2 +#define IXGBE_PCI_DEVICE_CONTROL2 0xC8 #define IXGBE_PCI_LINK_WIDTH 0x3F0 #define IXGBE_PCI_LINK_WIDTH_1 0x10 #define IXGBE_PCI_LINK_WIDTH_2 0x20 @@ -1532,6 +1539,7 @@ #define IXGBE_PCI_LINK_SPEED_5000 0x2 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 +#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 /* Number of 100 microseconds we wait for PCI Express master disable */ #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 |