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path: root/arch/arm/mach-mx6/cpu.c
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2011-11-10ENGR00161487: Fix SD/USB/FEC performance issue.er3-previewRanjani Vaidyanathan
When WAIT mode is not enabled, execute cpu_do_idle() code. Currently WAIT mode requires the code to be run from IRAM with caches disabled. No L2 cache access should be done for a specified period after the system exits WAIT mode. This delay and running code from IRAM adversely affects the SDHC performance. Hardware team is looking into the extended delay that is required. Till its root caused, default should be to execute cpu_do_idle() and disable entry into WAIT mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00161321 [MX6 ARM2]Disable Warm resetAnson Huang
Current warm reset is not working with MMDC_CH1 bypass bit set, now we disable warm reset to workaround it for the coming release. Then, wdog reset will be cold reset. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00160798 [MX6]Workaround for NFSAnson Huang
Disable SCU standby mode will prevent SOC enter WAIT mode, so, by default, we would not enable WAIT mode to make NFS work, to enable WAIT mode, you should not use NFS, and pass "enable_wait_mode" from uboot. Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00159641: MX6-Add DVFS-CORE supportRanjani Vaidyanathan
Add DVFS-CORE support for MX6 quad/dual SOC. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00155879: MX6: Enable ARM core to enter WAIT mode when system is idle.Ranjani Vaidyanathan
Set the appropriate bit in CCM to allow ARM-CORE to enter WAIT mode when system is idle. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00139280: MX6: Add CPUFREQ supportRanjani Vaidyanathan
Add support for CPUFREQ for SMP system. Added support for 1GHz, 800MHz, 400MHz and 160MHz. Added support for scaling the voltage along with frequency. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
2011-11-10ENGR00153429 [WDOG]Workaround for SMP wdog resetAnson Huang
1. Copy mx6_secondary_startup to iRAM; 2. CPU0 reset CPUx, then waiting CPUx reset OK, and clear CPUx's boot_entry; 3. CPUx reset OK, waiting CPU0 to clear its parameter; 4. All these steps done, CPUx go on boot; Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00139274-1 [MX6]Enable suspend/resume featureAnson Huang
Enable suspend/resume feature for MX6q echo standby > /sys/power/state -> wait mode; echo mem > /sys/power/state -> stop mode; Currentlu only support debug uart as wakeup source; Signed-off-by: Anson Huang <b20788@freescale.com>
2011-11-10ENGR00153132 mx6q: enable vpu iram usageSammy He
Enable iram for vpu on mx6q. Signed-off-by: Sammy He <r62914@freescale.com>
2011-11-10ENGR00139229-1 MX6: Bring up i.MX6 sabreauto with Single coreZeng Zhaoming
MSL code for bring up MX6 sabreauto board with Single core. Merged from testbuild:imx6_bringup branch. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com> Singed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Sammy He <r62914@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com> Merged-by: Zeng Zhaoming <b32542@freescale.com> Reviewed-by: Jason Liu <r64343@freescale.com> Reviewed-by: Frank Li <Frank.Li@freescale.com>