ENGR00155879: MX6: Enable ARM core to enter WAIT mode when system is idle.

Set the appropriate bit in CCM to allow ARM-CORE to enter WAIT
mode when system is idle.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

1 files changed, 35 insertions, 0 deletions

diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c
index dc3f1d16a02..ddc7b98f959 100644
--- a/arch/arm/mach-mx6/cpu.c
+++ b/arch/arm/mach-mx6/cpu.c
@@ -22,12 +22,22 @@
 #include <linux/clk.h>
 #include <linux/module.h>
 #include <linux/iram_alloc.h>
+#include <linux/delay.h>
+
 #include <mach/hardware.h>
 #include <asm/io.h>
+#include <asm/mach/map.h>
 
 #include "crm_regs.h"
 
+void *mx6_wait_in_iram_base;
+void (*mx6_wait_in_iram)(void *ccm_base);
+extern void mx6_wait(void);
+
+
 struct cpu_op *(*get_cpu_op)(int *op);
+static void __iomem *arm_base = IO_ADDRESS(MX6Q_A9_PLATFRM_BASE);
+
 
 int mx6_set_cpu_voltage(u32 cpu_volt)
 {
@@ -48,6 +58,8 @@ static int __init post_cpu_init(void)
 {
 	unsigned int reg;
 	void __iomem *base;
+	unsigned long iram_paddr, cpaddr;
+
 
 	iram_init(MX6Q_IRAM_BASE_ADDR, MX6Q_IRAM_SIZE);
 
@@ -69,6 +81,29 @@ static int __init post_cpu_init(void)
 	__raw_writel(reg, base + 0x50);
 	iounmap(base);
 
+	/* Allow SCU_CLK to be disabled when all cores are in WFI*/
+	base = IO_ADDRESS(SCU_BASE_ADDR);
+	reg = __raw_readl(base);
+	reg |= 0x20;
+	__raw_writel(reg, base);
+
+	/* Allocate IRAM for WAIT code. */
+	/* Move wait routine into iRAM */
+	cpaddr = (unsigned long)iram_alloc(SZ_4K, &iram_paddr);
+	/* Need to remap the area here since we want the memory region
+		 to be executable. */
+	mx6_wait_in_iram_base = __arm_ioremap(iram_paddr, SZ_4K,
+					  MT_MEMORY_NONCACHED);
+	pr_info("cpaddr = %x wait_iram_base=%x\n",
+		(unsigned int)cpaddr, (unsigned int)mx6_wait_in_iram_base);
+
+	/*
+	 * Need to run the suspend code from IRAM as the DDR needs
+	 * to be put into low power mode manually.
+	 */
+	memcpy((void *)cpaddr, mx6_wait, SZ_4K);
+	mx6_wait_in_iram = (void *)mx6_wait_in_iram_base;
+
 	return 0;
 }