diff options
| author | Anson Huang <b20788@freescale.com> | 2011-10-26 11:14:34 +0800 |
|---|---|---|
| committer | Eric Miao <eric.miao@canonical.com> | 2011-11-10 07:38:54 +0800 |
| commit | 58d3f53a39eca0dc64318bed7b18dd9de3a3520b (patch) | |
| tree | ac5002bafacc42a6b22965283b82ca836af278d3 /arch/arm/mach-mx6/cpu.c | |
| parent | 2f18a84207bd26d13820f2bb58b42ba7e8d15916 (diff) | |
ENGR00160798 [MX6]Workaround for NFS
Disable SCU standby mode will prevent SOC enter
WAIT mode, so, by default, we would not enable
WAIT mode to make NFS work, to enable WAIT mode,
you should not use NFS, and pass "enable_wait_mode"
from uboot.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/cpu.c')
| -rw-r--r-- | arch/arm/mach-mx6/cpu.c | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c index 46ac7da8cbe..66dde3c6a66 100644 --- a/arch/arm/mach-mx6/cpu.c +++ b/arch/arm/mach-mx6/cpu.c @@ -37,6 +37,7 @@ extern void mx6_wait(void); struct cpu_op *(*get_cpu_op)(int *op); static void __iomem *arm_base = IO_ADDRESS(MX6Q_A9_PLATFRM_BASE); +static bool enable_wait_mode; void __iomem *gpc_base; void __iomem *ccm_base; @@ -83,12 +84,13 @@ static int __init post_cpu_init(void) __raw_writel(reg, base + 0x50); iounmap(base); - /* Allow SCU_CLK to be disabled when all cores are in WFI*/ - base = IO_ADDRESS(SCU_BASE_ADDR); - reg = __raw_readl(base); - reg |= 0x20; - __raw_writel(reg, base); - + if (enable_wait_mode) { + /* Allow SCU_CLK to be disabled when all cores are in WFI*/ + base = IO_ADDRESS(SCU_BASE_ADDR); + reg = __raw_readl(base); + reg |= 0x20; + __raw_writel(reg, base); + } /* Allocate IRAM for WAIT code. */ /* Move wait routine into iRAM */ cpaddr = (unsigned long)iram_alloc(SZ_4K, &iram_paddr); @@ -111,5 +113,12 @@ static int __init post_cpu_init(void) return 0; } - postcore_initcall(post_cpu_init); + +static int __init enable_wait(char *p) +{ + enable_wait_mode = true; + return 0; +} +early_param("enable_wait_mode", enable_wait); + |