diff options
Diffstat (limited to 'arch/arm/mach-s5pc100')
26 files changed, 552 insertions, 728 deletions
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index b2a11dfa339..b8fbf2fcba6 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig @@ -9,7 +9,6 @@ if ARCH_S5PC100 config CPU_S5PC100 bool - select PLAT_S5P select S5P_EXT_INT select S3C_PL330_DMA help @@ -25,6 +24,16 @@ config S5PC100_SETUP_I2C1 help Common setup code for i2c bus 1. +config S5PC100_SETUP_IDE + bool + help + Common setup code for S5PC100 IDE GPIO configurations + +config S5PC100_SETUP_KEYPAD + bool + help + Common setup code for KEYPAD GPIO configurations. + config S5PC100_SETUP_SDHCI bool select S5PC100_SETUP_SDHCI_GPIO @@ -40,13 +49,24 @@ config MACH_SMDKC100 bool "SMDKC100" select CPU_S5PC100 select S3C_DEV_FB - select S3C_DEV_I2C1 select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 + select S3C_DEV_I2C1 + select S3C_DEV_RTC + select S3C_DEV_WDT + select SAMSUNG_DEV_ADC + select SAMSUNG_DEV_IDE + select SAMSUNG_DEV_KEYPAD + select SAMSUNG_DEV_TS select S5PC100_SETUP_FB_24BPP select S5PC100_SETUP_I2C1 + select S5PC100_SETUP_IDE + select S5PC100_SETUP_KEYPAD select S5PC100_SETUP_SDHCI + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 help Machine support for the Samsung SMDKC100 diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index 543f3de5131..eecab57d2e5 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile @@ -11,7 +11,7 @@ obj- := # Core support for S5PC100 system -obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o +obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o obj-$(CONFIG_CPU_S5PC100) += dma.o @@ -19,6 +19,8 @@ obj-$(CONFIG_CPU_S5PC100) += dma.o obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o +obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index e3fed4cfe7a..2d4a761a516 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -273,24 +273,6 @@ static struct clksrc_clk clk_div_hdmi = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, }; -static int s5pc100_epll_enable(struct clk *clk, int enable) -{ - unsigned int ctrlbit = clk->ctrlbit; - unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; - - if (enable) - __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); - else - __raw_writel(epll_con, S5P_EPLL_CON); - - return 0; -} - -static unsigned long s5pc100_epll_get_rate(struct clk *clk) -{ - return clk->rate; -} - static u32 epll_div[][4] = { { 32750000, 131, 3, 4 }, { 32768000, 131, 3, 4 }, @@ -341,13 +323,16 @@ static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate) __raw_writel(epll_con, S5P_EPLL_CON); + printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", + clk->rate, rate); + clk->rate = rate; return 0; } static struct clk_ops s5pc100_epll_ops = { - .get_rate = s5pc100_epll_get_rate, + .get_rate = s5p_epll_get_rate, .set_rate = s5pc100_epll_set_rate, }; @@ -691,55 +676,55 @@ static struct clk init_clocks_disable[] = { }, { .name = "iis", .id = 0, - .parent = &clk_div_d1_bus.clk, + .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 0), }, { .name = "iis", .id = 1, - .parent = &clk_div_d1_bus.clk, + .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 1), }, { .name = "iis", .id = 2, - .parent = &clk_div_d1_bus.clk, + .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 2), }, { .name = "ac97", .id = -1, - .parent = &clk_div_d1_bus.clk, + .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 3), }, { .name = "pcm", .id = 0, - .parent = &clk_div_d1_bus.clk, + .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 4), }, { .name = "pcm", .id = 1, - .parent = &clk_div_d1_bus.clk, + .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 5), }, { .name = "spdif", .id = -1, - .parent = &clk_div_d1_bus.clk, + .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 6), }, { .name = "adc", .id = -1, - .parent = &clk_div_d1_bus.clk, + .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 7), }, { - .name = "keyif", + .name = "keypad", .id = -1, - .parent = &clk_div_d1_bus.clk, + .parent = &clk_div_pclkd1.clk, .enable = s5pc100_d1_5_ctrl, .ctrlbit = (1 << 8), }, { @@ -848,6 +833,18 @@ struct clksrc_sources clk_src_group3 = { .nr_sources = ARRAY_SIZE(clk_src_group3_list), }; +static struct clksrc_clk clk_sclk_audio0 = { + .clk = { + .name = "sclk_audio", + .id = 0, + .ctrlbit = (1 << 8), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_group3, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, +}; + static struct clk *clk_src_group4_list[] = { [0] = &clk_mout_epll.clk, [1] = &clk_div_mpll.clk, @@ -862,6 +859,18 @@ struct clksrc_sources clk_src_group4 = { .nr_sources = ARRAY_SIZE(clk_src_group4_list), }; +static struct clksrc_clk clk_sclk_audio1 = { + .clk = { + .name = "sclk_audio", + .id = 1, + .ctrlbit = (1 << 9), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_group4, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, +}; + static struct clk *clk_src_group5_list[] = { [0] = &clk_mout_epll.clk, [1] = &clk_div_mpll.clk, @@ -875,6 +884,18 @@ struct clksrc_sources clk_src_group5 = { .nr_sources = ARRAY_SIZE(clk_src_group5_list), }; +static struct clksrc_clk clk_sclk_audio2 = { + .clk = { + .name = "sclk_audio", + .id = 2, + .ctrlbit = (1 << 10), + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clk_src_group5, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 }, + .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, +}; + static struct clk *clk_src_group6_list[] = { [0] = &s5p_clk_27m, [1] = &clk_vclk54m, @@ -944,6 +965,64 @@ struct clksrc_sources clk_src_pwi = { .nr_sources = ARRAY_SIZE(clk_src_pwi_list), }; +static struct clk *clk_sclk_spdif_list[] = { + [0] = &clk_sclk_audio0.clk, + [1] = &clk_sclk_audio1.clk, + [2] = &clk_sclk_audio2.clk, +}; + +struct clksrc_sources clk_src_sclk_spdif = { + .sources = clk_sclk_spdif_list, + .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list), +}; + +static int s5pc100_spdif_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *pclk; + int ret; + + pclk = clk_get_parent(clk); + if (IS_ERR(pclk)) + return -EINVAL; + + ret = pclk->ops->set_rate(pclk, rate); + clk_put(pclk); + + return ret; +} + +static unsigned long s5pc100_spdif_get_rate(struct clk *clk) +{ + struct clk *pclk; + int rate; + + pclk = clk_get_parent(clk); + if (IS_ERR(pclk)) + return -EINVAL; + + rate = pclk->ops->get_rate(clk); + clk_put(pclk); + + return rate; +} + +static struct clk_ops s5pc100_sclk_spdif_ops = { + .set_rate = s5pc100_spdif_set_rate, + .get_rate = s5pc100_spdif_get_rate, +}; + +static struct clksrc_clk clk_sclk_spdif = { + .clk = { + .name = "sclk_spdif", + .id = -1, + .ctrlbit = (1 << 11), + .enable = s5pc100_sclk1_ctrl, + .ops = &s5pc100_sclk_spdif_ops, + }, + .sources = &clk_src_sclk_spdif, + .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 }, +}; + static struct clksrc_clk clksrcs[] = { { .clk = { @@ -1001,39 +1080,6 @@ static struct clksrc_clk clksrcs[] = { .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 }, }, { .clk = { - .name = "sclk_audio", - .id = 0, - .ctrlbit = (1 << 8), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_group3, - .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, - }, { - .clk = { - .name = "sclk_audio", - .id = 1, - .ctrlbit = (1 << 9), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_group4, - .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, - }, { - .clk = { - .name = "sclk_audio", - .id = 2, - .ctrlbit = (1 << 10), - .enable = s5pc100_sclk1_ctrl, - - }, - .sources = &clk_src_group5, - .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 }, - .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, - }, { - .clk = { .name = "sclk_lcd", .id = -1, .ctrlbit = (1 << 0), @@ -1078,7 +1124,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 0, .ctrlbit = (1 << 12), .enable = s5pc100_sclk1_ctrl, @@ -1089,7 +1135,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 1, .ctrlbit = (1 << 13), .enable = s5pc100_sclk1_ctrl, @@ -1100,7 +1146,7 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, }, { .clk = { - .name = "mmc_bus", + .name = "sclk_mmc", .id = 2, .ctrlbit = (1 << 14), .enable = s5pc100_sclk1_ctrl, @@ -1179,6 +1225,10 @@ static struct clksrc_clk *sysclks[] = { &clk_div_pclkd1, &clk_div_cam, &clk_div_hdmi, + &clk_sclk_audio0, + &clk_sclk_audio1, + &clk_sclk_audio2, + &clk_sclk_spdif, }; void __init_or_cpufreq s5pc100_setup_clocks(void) @@ -1196,7 +1246,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) unsigned int ptr; /* Set S5PC100 functions for clk_fout_epll */ - clk_fout_epll.enable = s5pc100_epll_enable; + clk_fout_epll.enable = s5p_epll_enable; clk_fout_epll.ops = &s5pc100_epll_ops; printk(KERN_DEBUG "%s: registering clocks\n", __func__); diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c index 7b5bdbc9a5d..fd2708e7d8a 100644 --- a/arch/arm/mach-s5pc100/cpu.c +++ b/arch/arm/mach-s5pc100/cpu.c @@ -1,5 +1,8 @@ /* linux/arch/arm/mach-s5pc100/cpu.c * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * * Copyright 2009 Samsung Electronics Co. * Byungho Min <bhmin@samsung.com> * @@ -21,6 +24,7 @@ #include <linux/sysdev.h> #include <linux/serial_core.h> #include <linux/platform_device.h> +#include <linux/sched.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -38,9 +42,12 @@ #include <plat/cpu.h> #include <plat/devs.h> #include <plat/clock.h> +#include <plat/ata-core.h> #include <plat/iic-core.h> #include <plat/sdhci.h> +#include <plat/adc-core.h> #include <plat/onenand-core.h> +#include <plat/fb-core.h> #include <plat/s5pc100.h> @@ -53,11 +60,31 @@ static struct map_desc s5pc100_iodesc[] __initdata = { .length = SZ_16K, .type = MT_DEVICE, }, { + .virtual = (unsigned long)S5P_VA_GPIO, + .pfn = __phys_to_pfn(S5PC100_PA_GPIO), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC0, + .pfn = __phys_to_pfn(S5PC100_PA_VIC0), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)VA_VIC1, + .pfn = __phys_to_pfn(S5PC100_PA_VIC1), + .length = SZ_16K, + .type = MT_DEVICE, + }, { .virtual = (unsigned long)VA_VIC2, - .pfn = __phys_to_pfn(S5P_PA_VIC2), + .pfn = __phys_to_pfn(S5PC100_PA_VIC2), .length = SZ_16K, .type = MT_DEVICE, }, { + .virtual = (unsigned long)S3C_VA_UART, + .pfn = __phys_to_pfn(S3C_PA_UART), + .length = SZ_512K, + .type = MT_DEVICE, + }, { .virtual = (unsigned long)S5PC100_VA_OTHERS, .pfn = __phys_to_pfn(S5PC100_PA_OTHERS), .length = SZ_4K, @@ -87,11 +114,15 @@ void __init s5pc100_map_io(void) s5pc100_default_sdhci1(); s5pc100_default_sdhci2(); + s3c_adc_setname("s3c64xx-adc"); + /* the i2c devices are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); s3c_onenand_setname("s5pc100-onenand"); + s3c_fb_setname("s5pc100-fb"); + s3c_cfcon_setname("s5pc100-pata"); } void __init s5pc100_init_clocks(int xtal) diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c index 18cfe9ae193..564e195ec49 100644 --- a/arch/arm/mach-s5pc100/dev-audio.c +++ b/arch/arm/mach-s5pc100/dev-audio.c @@ -10,11 +10,11 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <plat/gpio-cfg.h> #include <plat/audio.h> -#include <mach/gpio.h> #include <mach/map.h> #include <mach/dma.h> #include <mach/irqs.h> @@ -24,19 +24,11 @@ static int s5pc100_cfg_i2s(struct platform_device *pdev) /* configure GPIO for i2s port */ switch (pdev->id) { case 1: - s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2)); + s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2)); break; case 2: - s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4)); + s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4)); break; case -1: /* Dedicated pins */ @@ -144,19 +136,11 @@ static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev) { switch (pdev->id) { case 0: - s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5)); - s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5)); - s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5)); - s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5)); - s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5)); + s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5)); break; case 1: - s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3)); + s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3)); break; default: @@ -231,13 +215,7 @@ struct platform_device s5pc100_device_pcm1 = { static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev) { - s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4)); - s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4)); - - return 0; + return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4)); } static struct resource s5pc100_ac97_resource[] = { @@ -285,3 +263,57 @@ struct platform_device s5pc100_device_ac97 = { .coherent_dma_mask = DMA_BIT_MASK(32), }, }; + +/* S/PDIF Controller platform_device */ +static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev) +{ + s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3)); + + return 0; +} + +static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev) +{ + s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3)); + + return 0; +} + +static struct resource s5pc100_spdif_resource[] = { + [0] = { + .start = S5PC100_PA_SPDIF, + .end = S5PC100_PA_SPDIF + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPDIF, + .end = DMACH_SPDIF, + .flags = IORESOURCE_DMA, + }, +}; + +static struct s3c_audio_pdata s5p_spdif_pdata = { + .cfg_gpio = s5pc100_spdif_cfg_gpd, +}; + +static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32); + +struct platform_device s5pc100_device_spdif = { + .name = "samsung-spdif", + .id = -1, + .num_resources = ARRAY_SIZE(s5pc100_spdif_resource), + .resource = s5pc100_spdif_resource, + .dev = { + .platform_data = &s5p_spdif_pdata, + .dma_mask = &s5pc100_spdif_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init s5pc100_spdif_setup_gpio(int gpio) +{ + if (gpio == S5PC100_SPDIF_GPD) + s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd; + else + s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3; +} diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c index 14618c34605..57b19794d9b 100644 --- a/arch/arm/mach-s5pc100/dev-spi.c +++ b/arch/arm/mach-s5pc100/dev-spi.c @@ -10,10 +10,10 @@ #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpio.h> #include <mach/dma.h> #include <mach/map.h> -#include <mach/gpio.h> #include <mach/spi-clocks.h> #include <plat/s3c64xx-spi.h> @@ -38,30 +38,20 @@ static int s5pc100_spi_cfg_gpio(struct platform_device *pdev) { switch (pdev->id) { case 0: - s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); break; case 1: - s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2)); - s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); break; case 2: s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3)); - s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3)); s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP); - s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PC100_GPB(2), 2, + S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); break; default: diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c index 0f5517571e2..bf4cd0fb97c 100644 --- a/arch/arm/mach-s5pc100/dma.c +++ b/arch/arm/mach-s5pc100/dma.c @@ -81,7 +81,7 @@ static struct s3c_pl330_platdata s5pc100_pdma0_pdata = { static struct platform_device s5pc100_device_pdma0 = { .name = "s3c-pl330", - .id = 1, + .id = 0, .num_resources = ARRAY_SIZE(s5pc100_pdma0_resource), .resource = s5pc100_pdma0_resource, .dev = { @@ -143,7 +143,7 @@ static struct s3c_pl330_platdata s5pc100_pdma1_pdata = { static struct platform_device s5pc100_device_pdma1 = { .name = "s3c-pl330", - .id = 2, + .id = 1, .num_resources = ARRAY_SIZE(s5pc100_pdma1_resource), .resource = s5pc100_pdma1_resource, .dev = { diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c index 0fab7f2cd8b..20856eb7dd5 100644 --- a/arch/arm/mach-s5pc100/gpiolib.c +++ b/arch/arm/mach-s5pc100/gpiolib.c @@ -1,5 +1,7 @@ -/* - * arch/arm/plat-s5pc100/gpiolib.c +/* linux/arch/arm/mach-s5pc100/gpiolib.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com * * Copyright 2009 Samsung Electronics Co * Kyungmin Park <kyungmin.park@samsung.com> @@ -61,30 +63,6 @@ * L3 8 4Bit None */ -static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) -{ - return S3C_IRQ_GPIO(chip->base + offset); -} - -static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) -{ - int base; - - base = chip->base - S5PC100_GPH0(0); - if (base == 0) - return IRQ_EINT(offset); - base = chip->base - S5PC100_GPH1(0); - if (base == 0) - return IRQ_EINT(8 + offset); - base = chip->base - S5PC100_GPH2(0); - if (base == 0) - return IRQ_EINT(16 + offset); - base = chip->base - S5PC100_GPH3(0); - if (base == 0) - return IRQ_EINT(24 + offset); - return -EINVAL; -} - static struct s3c_gpio_cfg gpio_cfg = { .set_config = s3c_gpio_setcfg_s3c64xx_4bit, .set_pull = s3c_gpio_setpull_updown, @@ -104,209 +82,150 @@ static struct s3c_gpio_cfg gpio_cfg_noint = { .get_pull = s3c_gpio_getpull_updown, }; +/* + * GPIO bank's base address given the index of the bank in the + * list of all gpio banks. + */ +#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) + +/* + * Following are the gpio banks in S5PC100. + * + * The 'config' member when left to NULL, is initialized to the default + * structure gpio_cfg in the init function below. + * + * The 'base' member is also initialized in the init function below. + * Note: The initialization of 'base' member of s3c_gpio_chip structure + * uses the above macro and depends on the banks being listed in order here. + */ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { { - .base = S5PC100_GPA0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPA0(0), .ngpio = S5PC100_GPIO_A0_NR, .label = "GPA0", }, }, { - .base = S5PC100_GPA1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPA1(0), .ngpio = S5PC100_GPIO_A1_NR, .label = "GPA1", }, }, { - .base = S5PC100_GPB_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPB(0), .ngpio = S5PC100_GPIO_B_NR, .label = "GPB", }, }, { - .base = S5PC100_GPC_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPC(0), .ngpio = S5PC100_GPIO_C_NR, .label = "GPC", }, }, { - .base = S5PC100_GPD_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPD(0), .ngpio = S5PC100_GPIO_D_NR, .label = "GPD", }, }, { - .base = S5PC100_GPE0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPE0(0), .ngpio = S5PC100_GPIO_E0_NR, .label = "GPE0", }, }, { - .base = S5PC100_GPE1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPE1(0), .ngpio = S5PC100_GPIO_E1_NR, .label = "GPE1", }, }, { - .base = S5PC100_GPF0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPF0(0), .ngpio = S5PC100_GPIO_F0_NR, .label = "GPF0", }, }, { - .base = S5PC100_GPF1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPF1(0), .ngpio = S5PC100_GPIO_F1_NR, .label = "GPF1", }, }, { - .base = S5PC100_GPF2_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPF2(0), .ngpio = S5PC100_GPIO_F2_NR, .label = "GPF2", }, }, { - .base = S5PC100_GPF3_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPF3(0), .ngpio = S5PC100_GPIO_F3_NR, .label = "GPF3", }, }, { - .base = S5PC100_GPG0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPG0(0), .ngpio = S5PC100_GPIO_G0_NR, .label = "GPG0", }, }, { - .base = S5PC100_GPG1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPG1(0), .ngpio = S5PC100_GPIO_G1_NR, .label = "GPG1", }, }, { - .base = S5PC100_GPG2_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPG2(0), .ngpio = S5PC100_GPIO_G2_NR, .label = "GPG2", }, }, { - .base = S5PC100_GPG3_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPG3(0), .ngpio = S5PC100_GPIO_G3_NR, .label = "GPG3", }, }, { - .base = S5PC100_GPH0_BASE, - .config = &gpio_cfg_eint, - .chip = { - .base = S5PC100_GPH0(0), - .ngpio = S5PC100_GPIO_H0_NR, - .label = "GPH0", - }, - }, { - .base = S5PC100_GPH1_BASE, - .config = &gpio_cfg_eint, - .chip = { - .base = S5PC100_GPH1(0), - .ngpio = S5PC100_GPIO_H1_NR, - .label = "GPH1", - }, - }, { - .base = S5PC100_GPH2_BASE, - .config = &gpio_cfg_eint, - .chip = { - .base = S5PC100_GPH2(0), - .ngpio = S5PC100_GPIO_H2_NR, - .label = "GPH2", - }, - }, { - .base = S5PC100_GPH3_BASE, - .config = &gpio_cfg_eint, - .chip = { - .base = S5PC100_GPH3(0), - .ngpio = S5PC100_GPIO_H3_NR, - .label = "GPH3", - }, - }, { - .base = S5PC100_GPI_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPI(0), .ngpio = S5PC100_GPIO_I_NR, .label = "GPI", }, }, { - .base = S5PC100_GPJ0_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ0(0), .ngpio = S5PC100_GPIO_J0_NR, .label = "GPJ0", }, }, { - .base = S5PC100_GPJ1_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ1(0), .ngpio = S5PC100_GPIO_J1_NR, .label = "GPJ1", }, }, { - .base = S5PC100_GPJ2_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ2(0), .ngpio = S5PC100_GPIO_J2_NR, .label = "GPJ2", }, }, { - .base = S5PC100_GPJ3_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ3(0), .ngpio = S5PC100_GPIO_J3_NR, .label = "GPJ3", }, }, { - .base = S5PC100_GPJ4_BASE, - .config = &gpio_cfg, .chip = { .base = S5PC100_GPJ4(0), .ngpio = S5PC100_GPIO_J4_NR, .label = "GPJ4", }, }, { - .base = S5PC100_GPK0_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPK0(0), @@ -314,7 +233,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPK0", }, }, { - .base = S5PC100_GPK1_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPK1(0), @@ -322,7 +240,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPK1", }, }, { - .base = S5PC100_GPK2_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPK2(0), @@ -330,7 +247,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPK2", }, }, { - .base = S5PC100_GPK3_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPK3(0), @@ -338,7 +254,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPK3", }, }, { - .base = S5PC100_GPL0_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL0(0), @@ -346,7 +261,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPL0", }, }, { - .base = S5PC100_GPL1_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL1(0), @@ -354,7 +268,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPL1", }, }, { - .base = S5PC100_GPL2_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL2(0), @@ -362,7 +275,6 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPL2", }, }, { - .base = S5PC100_GPL3_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL3(0), @@ -370,56 +282,72 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { .label = "GPL3", }, }, { - .base = S5PC100_GPL4_BASE, .config = &gpio_cfg_noint, .chip = { .base = S5PC100_GPL4(0), .ngpio = S5PC100_GPIO_L4_NR, .label = "GPL4", }, + }, { + .base = (S5P_VA_GPIO + 0xC00), + .config = &gpio_cfg_eint, + .irq_base = IRQ_EINT(0), + .chip = { + .base = S5PC100_GPH0(0), + .ngpio = S5PC100_GPIO_H0_NR, + .label = "GPH0", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC20), + .config = &gpio_cfg_eint, + .irq_base = IRQ_EINT(8), + .chip = { + .base = S5PC100_GPH1(0), + .ngpio = S5PC100_GPIO_H1_NR, + .label = "GPH1", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC40), + .config = &gpio_cfg_eint, + .irq_base = IRQ_EINT(16), + .chip = { + .base = S5PC100_GPH2(0), + .ngpio = S5PC100_GPIO_H2_NR, + .label = "GPH2", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC60), + .config = &gpio_cfg_eint, + .irq_base = IRQ_EINT(24), + .chip = { + .base = S5PC100_GPH3(0), + .ngpio = S5PC100_GPIO_H3_NR, + .label = "GPH3", + .to_irq = samsung_gpiolib_to_irq, + }, }, }; -/* FIXME move from irq-gpio.c */ -extern struct irq_chip s5pc100_gpioint; -extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); - -static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) +static __init int s5pc100_gpiolib_init(void) { - /* Interrupt */ - if (chip->config == &gpio_cfg) { - int i, irq; - - chip->chip.to_irq = s5pc100_gpiolib_to_irq; + struct s3c_gpio_chip *chip = s5pc100_gpio_chips; + int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); + int gpioint_group = 0; + int i; - for (i = 0; i < chip->chip.ngpio; i++) { - irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; - set_irq_chip(irq, &s5pc100_gpioint); - set_irq_data(irq, &chip->chip); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); + for (i = 0; i < nr_chips; i++, chip++) { + if (chip->config == NULL) { + chip->config = &gpio_cfg; + chip->group = gpioint_group++; } - } else if (chip->config == &gpio_cfg_eint) { - chip->chip.to_irq = s5pc100_gpiolib_to_eint; + if (chip->base == NULL) + chip->base = S5PC100_BANK_BASE(i); } -} - -static __init int s5pc100_gpiolib_init(void) -{ - struct s3c_gpio_chip *chip; - int nr_chips; - - chip = s5pc100_gpio_chips; - nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); - - for (; nr_chips > 0; nr_chips--, chip++) - s5pc100_gpiolib_link(chip); - - samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, - ARRAY_SIZE(s5pc100_gpio_chips)); - /* Interrupt */ - set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler); + samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips); return 0; } diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S index 70e02e91ee3..b2ba95ddf8e 100644 --- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S +++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S @@ -22,13 +22,12 @@ * aligned and add in the offset when we load the value here. */ - .macro addruart, rx, rtmp - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 - ldreq \rx, = S3C_PA_UART - ldrne \rx, = S3C_VA_UART + .macro addruart, rp, rv + ldr \rp, = S3C_PA_UART + ldr \rv, = S3C_VA_UART #if CONFIG_DEBUG_S3C_UART != 0 - add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) + add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART) + add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART) #endif .endm diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h index 71ae1f52df1..29a8a12d9b4 100644 --- a/arch/arm/mach-s5pc100/include/mach/gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h @@ -146,13 +146,6 @@ enum s5p_gpio_number { /* define the number of gpios we need to the one after the MP04() range */ #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) -#define EINT_MODE S3C_GPIO_SFN(0x2) - -#define EINT_GPIO_0(x) S5PC100_GPH0(x) -#define EINT_GPIO_1(x) S5PC100_GPH1(x) -#define EINT_GPIO_2(x) S5PC100_GPH2(x) -#define EINT_GPIO_3(x) S5PC100_GPH3(x) - #include <asm-generic/gpio.h> #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index 28aa551dc3a..d2eb4757381 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h @@ -29,7 +29,7 @@ #define IRQ_GPIOINT S5P_IRQ_VIC0(30) /* VIC1: ARM, power, memory, connectivity */ -#define IRQ_CORTEX0 S5P_IRQ_VIC1(0) +#define IRQ_PMU S5P_IRQ_VIC1(0) #define IRQ_CORTEX1 S5P_IRQ_VIC1(1) #define IRQ_CORTEX2 S5P_IRQ_VIC1(2) #define IRQ_CORTEX3 S5P_IRQ_VIC1(3) @@ -38,7 +38,7 @@ #define IRQ_IEMIEC S5P_IRQ_VIC1(6) #define IRQ_ONENAND S5P_IRQ_VIC1(7) #define IRQ_NFC S5P_IRQ_VIC1(8) -#define IRQ_CFC S5P_IRQ_VIC1(9) +#define IRQ_CFCON S5P_IRQ_VIC1(9) #define IRQ_UART0 S5P_IRQ_VIC1(10) #define IRQ_UART1 S5P_IRQ_VIC1(11) #define IRQ_UART2 S5P_IRQ_VIC1(12) @@ -48,8 +48,8 @@ #define IRQ_SPI1 S5P_IRQ_VIC1(16) #define IRQ_SPI2 S5P_IRQ_VIC1(17) #define IRQ_IRDA S5P_IRQ_VIC1(18) -#define IRQ_CAN0 S5P_IRQ_VIC1(19) -#define IRQ_CAN1 S5P_IRQ_VIC1(20) +#define IRQ_IIC2 S5P_IRQ_VIC1(19) +#define IRQ_IIC3 S5P_IRQ_VIC1(20) #define IRQ_HSIRX S5P_IRQ_VIC1(21) #define IRQ_HSITX S5P_IRQ_VIC1(22) #define IRQ_UHOST S5P_IRQ_VIC1(23) @@ -100,11 +100,12 @@ #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) -#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) -#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) +/* GPIO interrupt */ +#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1) +#define S5P_GPIOINT_GROUP_MAXNR 21 -/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */ -#define NR_IRQS (S3C_IRQ_GPIO(320) + 1) +/* Set the default NR_IRQS */ +#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1) /* Compatibility */ #define IRQ_LCD_FIFO IRQ_LCD0 diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index cadae430568..32e9cab5c86 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -44,23 +44,22 @@ #define S5PC100_PA_OTHERS (0xE0200000) #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) -#define S5P_PA_GPIO (0xE0300000) +#define S5PC100_PA_GPIO (0xE0300000) #define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) /* Interrupt */ -#define S5PC100_PA_VIC (0xE4000000) +#define S5PC100_PA_VIC0 (0xE4000000) +#define S5PC100_PA_VIC1 (0xE4100000) +#define S5PC100_PA_VIC2 (0xE4200000) #define S5PC100_VA_VIC S3C_VA_IRQ -#define S5PC100_PA_VIC_OFFSET 0x100000 #define S5PC100_VA_VIC_OFFSET 0x10000 -#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) -#define S5P_PA_VIC0 S5PC1XX_PA_VIC(0) -#define S5P_PA_VIC1 S5PC1XX_PA_VIC(1) -#define S5P_PA_VIC2 S5PC1XX_PA_VIC(2) #define S5PC100_PA_ONENAND (0xE7100000) +#define S5PC100_PA_CFCON (0xE7800000) + /* DMA */ #define S5PC100_PA_MDMA (0xE8100000) #define S5PC100_PA_PDMA0 (0xE9000000) @@ -72,6 +71,9 @@ #define S5PC100_PA_SYSTIMER (0xEA100000) +#define S5PC100_PA_WATCHDOG (0xEA200000) +#define S5PC100_PA_RTC (0xEA300000) + #define S5PC100_PA_UART (0xEC000000) #define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) @@ -94,6 +96,10 @@ #define S5PC100_PA_FB (0xEE000000) +#define S5PC100_PA_FIMC0 (0xEE200000) +#define S5PC100_PA_FIMC1 (0xEE300000) +#define S5PC100_PA_FIMC2 (0xEE400000) + #define S5PC100_PA_I2S0 (0xF2000000) #define S5PC100_PA_I2S1 (0xF2100000) #define S5PC100_PA_I2S2 (0xF2200000) @@ -104,6 +110,10 @@ #define S5PC100_PA_PCM0 0xF2400000 #define S5PC100_PA_PCM1 0xF2500000 +#define S5PC100_PA_SPDIF 0xF2600000 + +#define S5PC100_PA_TSADC (0xF3000000) + /* KEYPAD */ #define S5PC100_PA_KEYPAD (0xF3100000) @@ -130,9 +140,19 @@ #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD +#define S3C_PA_WDT S5PC100_PA_WATCHDOG #define S3C_PA_TSADC S5PC100_PA_TSADC #define S3C_PA_ONENAND S5PC100_PA_ONENAND #define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF #define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF +#define S3C_PA_RTC S5PC100_PA_RTC + +#define SAMSUNG_PA_ADC S5PC100_PA_TSADC +#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON +#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD + +#define S5P_PA_FIMC0 S5PC100_PA_FIMC0 +#define S5P_PA_FIMC1 S5PC100_PA_FIMC1 +#define S5P_PA_FIMC2 S5PC100_PA_FIMC2 #endif /* __ASM_ARCH_C100_MAP_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h index 5d27d286d50..bc92da2e0ba 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h @@ -71,7 +71,10 @@ #define S5P_CLKDIV1_PCLKD1_SHIFT (16) #define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000) +#define S5PC100_MEM_SYS_CFG S5PC100_REG_OTHERS(0x200) #define S5PC100_SWRESET_RESETVAL 0xc100 +#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 + #endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h index 1732cd28c76..4be4cc9abf7 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h @@ -100,40 +100,6 @@ #define BLENDCON (0x260) #define BLENDCON_8BIT_ALPHA (1 << 0) -/* Per-window palette base addresses (start of palette memory). - * Each window palette area consists of 256 32-bit entries. - * START is the first address (entry 0th), END is the address of 255th entry. - */ -#define WIN0_PAL_BASE (0x2400) -#define WIN0_PAL_END (0x27fc) -#define WIN1_PAL_BASE (0x2800) -#define WIN1_PAL_END (0x2bfc) -#define WIN2_PAL_BASE (0x2c00) -#define WIN2_PAL_END (0x2ffc) -#define WIN3_PAL_BASE (0x3000) -#define WIN3_PAL_END (0x33fc) -#define WIN4_PAL_BASE (0x3400) -#define WIN4_PAL_END (0x37fc) - -#define WIN0_PAL(_entry) (WIN0_PAL_BASE + ((_entry) * 4)) -#define WIN1_PAL(_entry) (WIN1_PAL_BASE + ((_entry) * 4)) -#define WIN2_PAL(_entry) (WIN2_PAL_BASE + ((_entry) * 4)) -#define WIN3_PAL(_entry) (WIN3_PAL_BASE + ((_entry) * 4)) -#define WIN4_PAL(_entry) (WIN4_PAL_BASE + ((_entry) * 4)) - -static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) -{ - switch (window) { - case 0: return WIN0_PAL(reg); - case 1: return WIN1_PAL(reg); - case 2: return WIN2_PAL(reg); - case 3: return WIN3_PAL(reg); - case 4: return WIN4_PAL(reg); - } - - BUG(); -} - #endif /* __ASM_ARCH_REGS_FB_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h index dd6295e1251..0bf73209ec7 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h @@ -11,43 +11,6 @@ #include <mach/map.h> -/* S5PC100 */ -#define S5PC100_GPIO_BASE S5P_VA_GPIO -#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) -#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) -#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) -#define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060) -#define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080) -#define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0) -#define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0) -#define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0) -#define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100) -#define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120) -#define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140) -#define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160) -#define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180) -#define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0) -#define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0) -#define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00) -#define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20) -#define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40) -#define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60) -#define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0) -#define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200) -#define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220) -#define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240) -#define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260) -#define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280) -#define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0) -#define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0) -#define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0) -#define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300) -#define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320) -#define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340) -#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) -#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) -#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) - #define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00) #define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4)) @@ -64,12 +27,12 @@ #define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) -/* values for S5P_EXTINT0 */ -#define S5P_EXTINT_LOWLEV (0x00) -#define S5P_EXTINT_HILEV (0x01) -#define S5P_EXTINT_FALLEDGE (0x02) -#define S5P_EXTINT_RISEEDGE (0x03) -#define S5P_EXTINT_BOTHEDGE (0x04) +#define EINT_MODE S3C_GPIO_SFN(0x2) + +#define EINT_GPIO_0(x) S5PC100_GPH0(x) +#define EINT_GPIO_1(x) S5PC100_GPH1(x) +#define EINT_GPIO_2(x) S5PC100_GPH2(x) +#define EINT_GPIO_3(x) S5PC100_GPH3(x) #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h index 681f626a9ae..a9ea57c0660 100644 --- a/arch/arm/mach-s5pc100/include/mach/system.h +++ b/arch/arm/mach-s5pc100/include/mach/system.h @@ -11,18 +11,11 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ -#include <linux/io.h> -#include <mach/map.h> -#include <mach/regs-clock.h> +#include <plat/system-reset.h> static void arch_idle(void) { /* nothing here yet */ } -static void arch_reset(char mode, const char *cmd) -{ - __raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET); - return; -} #endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/vmalloc.h b/arch/arm/mach-s5pc100/include/mach/vmalloc.h index be9df79903e..44c8e5726d9 100644 --- a/arch/arm/mach-s5pc100/include/mach/vmalloc.h +++ b/arch/arm/mach-s5pc100/include/mach/vmalloc.h @@ -12,6 +12,6 @@ #ifndef __ASM_ARCH_VMALLOC_H #define __ASM_ARCH_VMALLOC_H -#define VMALLOC_END (0xe0000000UL) +#define VMALLOC_END 0xF6000000UL #endif /* __ASM_ARCH_VMALLOC_H */ diff --git a/arch/arm/mach-s5pc100/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c deleted file mode 100644 index 2bf86c18bc7..00000000000 --- a/arch/arm/mach-s5pc100/irq-gpio.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * arch/arm/mach-s5pc100/irq-gpio.c - * - * Copyright (C) 2009 Samsung Electronics - * - * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <mach/map.h> -#include <plat/gpio-cfg.h> - -#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x)) - -#define CON_OFFSET 0x700 -#define MASK_OFFSET 0x900 -#define PEND_OFFSET 0xA00 -#define CON_OFFSET_2 0xE00 -#define MASK_OFFSET_2 0xF00 -#define PEND_OFFSET_2 0xF40 - -#define GPIOINT_LEVEL_LOW 0x0 -#define GPIOINT_LEVEL_HIGH 0x1 -#define GPIOINT_EDGE_FALLING 0x2 -#define GPIOINT_EDGE_RISING 0x3 -#define GPIOINT_EDGE_BOTH 0x4 - -static int group_to_con_offset(int group) -{ - return group << 2; -} - -static int group_to_mask_offset(int group) -{ - return group << 2; -} - -static int group_to_pend_offset(int group) -{ - return group << 2; -} - -static int s5pc100_get_start(unsigned int group) -{ - switch (group) { - case 0: return S5PC100_GPIO_A0_START; - case 1: return S5PC100_GPIO_A1_START; - case 2: return S5PC100_GPIO_B_START; - case 3: return S5PC100_GPIO_C_START; - case 4: return S5PC100_GPIO_D_START; - case 5: return S5PC100_GPIO_E0_START; - case 6: return S5PC100_GPIO_E1_START; - case 7: return S5PC100_GPIO_F0_START; - case 8: return S5PC100_GPIO_F1_START; - case 9: return S5PC100_GPIO_F2_START; - case 10: return S5PC100_GPIO_F3_START; - case 11: return S5PC100_GPIO_G0_START; - case 12: return S5PC100_GPIO_G1_START; - case 13: return S5PC100_GPIO_G2_START; - case 14: return S5PC100_GPIO_G3_START; - case 15: return S5PC100_GPIO_I_START; - case 16: return S5PC100_GPIO_J0_START; - case 17: return S5PC100_GPIO_J1_START; - case 18: return S5PC100_GPIO_J2_START; - case 19: return S5PC100_GPIO_J3_START; - case 20: return S5PC100_GPIO_J4_START; - default: - BUG(); - } - - return -EINVAL; -} - -static int s5pc100_get_group(unsigned int irq) -{ - irq -= S3C_IRQ_GPIO(0); - - switch (irq) { - case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1: - return 0; - case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1: - return 1; - case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1: - return 2; - case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1: - return 3; - case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1: - return 4; - case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1: - return 5; - case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1: - return 6; - case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1: - return 7; - case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1: - return 8; - case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1: - return 9; - case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1: - return 10; - case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1: - return 11; - case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1: - return 12; - case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1: - return 13; - case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1: - return 14; - case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1: - return 15; - case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1: - return 16; - case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1: - return 17; - case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1: - return 18; - case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1: - return 19; - case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1: - return 20; - default: - BUG(); - } - - return -EINVAL; -} - -static int s5pc100_get_offset(unsigned int irq) -{ - struct gpio_chip *chip = get_irq_data(irq); - return irq - S3C_IRQ_GPIO(chip->base); -} - -static void s5pc100_gpioint_ack(unsigned int irq) -{ - int group, offset, pend_offset; - unsigned int value; - - group = s5pc100_get_group(irq); - offset = s5pc100_get_offset(irq); - pend_offset = group_to_pend_offset(group); - - value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset); - value |= 1 << offset; - __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset); -} - -static void s5pc100_gpioint_mask(unsigned int irq) -{ - int group, offset, mask_offset; - unsigned int value; - - group = s5pc100_get_group(irq); - offset = s5pc100_get_offset(irq); - mask_offset = group_to_mask_offset(group); - - value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); - value |= 1 << offset; - __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset); -} - -static void s5pc100_gpioint_unmask(unsigned int irq) -{ - int group, offset, mask_offset; - unsigned int value; - - group = s5pc100_get_group(irq); - offset = s5pc100_get_offset(irq); - mask_offset = group_to_mask_offset(group); - - value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); - value &= ~(1 << offset); - __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset); -} - -static void s5pc100_gpioint_mask_ack(unsigned int irq) -{ - s5pc100_gpioint_mask(irq); - s5pc100_gpioint_ack(irq); -} - -static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type) -{ - int group, offset, con_offset; - unsigned int value; - - group = s5pc100_get_group(irq); - offset = s5pc100_get_offset(irq); - con_offset = group_to_con_offset(group); - - switch (type) { - case IRQ_TYPE_NONE: - printk(KERN_WARNING "No irq type\n"); - return -EINVAL; - case IRQ_TYPE_EDGE_RISING: - type = GPIOINT_EDGE_RISING; - break; - case IRQ_TYPE_EDGE_FALLING: - type = GPIOINT_EDGE_FALLING; - break; - case IRQ_TYPE_EDGE_BOTH: - type = GPIOINT_EDGE_BOTH; - break; - case IRQ_TYPE_LEVEL_HIGH: - type = GPIOINT_LEVEL_HIGH; - break; - case IRQ_TYPE_LEVEL_LOW: - type = GPIOINT_LEVEL_LOW; - break; - default: - BUG(); - } - - - value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset); - value &= ~(0xf << (offset * 0x4)); - value |= (type << (offset * 0x4)); - __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset); - - return 0; -} - -struct irq_chip s5pc100_gpioint = { - .name = "GPIO", - .ack = s5pc100_gpioint_ack, - .mask = s5pc100_gpioint_mask, - .mask_ack = s5pc100_gpioint_mask_ack, - .unmask = s5pc100_gpioint_unmask, - .set_type = s5pc100_gpioint_set_type, -}; - -void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) -{ - int group, offset, pend_offset, mask_offset; - int real_irq, group_end; - unsigned int pend, mask; - - group_end = 21; - - for (group = 0; group < group_end; group++) { - pend_offset = group_to_pend_offset(group); - pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset); - if (!pend) - continue; - - mask_offset = group_to_mask_offset(group); - mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); - pend &= ~mask; - - for (offset = 0; offset < 8; offset++) { - if (pend & (1 << offset)) { - real_irq = s5pc100_get_start(group) + offset; - generic_handle_irq(S3C_IRQ_GPIO(real_irq)); - } - } - } -} diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index af22f8202a0..18b405d514d 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -22,6 +22,7 @@ #include <linux/i2c.h> #include <linux/fb.h> #include <linux/delay.h> +#include <linux/input.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -42,18 +43,23 @@ #include <plat/s5pc100.h> #include <plat/fb.h> #include <plat/iic.h> +#include <plat/ata.h> +#include <plat/adc.h> +#include <plat/keypad.h> +#include <plat/ts.h> +#include <plat/audio.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ -#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ +#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ S3C2410_UCON_TXIRQMODE | \ S3C2410_UCON_RXIRQMODE | \ S3C2410_UCON_RXFIFO_TOI | \ S3C2443_UCON_RXERR_IRQEN) -#define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 +#define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8 -#define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ +#define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ S3C2440_UFCON_RXTRIG8 | \ S3C2440_UFCON_TXTRIG16) @@ -61,30 +67,30 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { [0] = { .hwport = 0, .flags = 0, - .ucon = S5PC100_UCON_DEFAULT, - .ulcon = S5PC100_ULCON_DEFAULT, - .ufcon = S5PC100_UFCON_DEFAULT, + .ucon = SMDKC100_UCON_DEFAULT, + .ulcon = SMDKC100_ULCON_DEFAULT, + .ufcon = SMDKC100_UFCON_DEFAULT, }, [1] = { .hwport = 1, .flags = 0, - .ucon = S5PC100_UCON_DEFAULT, - .ulcon = S5PC100_ULCON_DEFAULT, - .ufcon = S5PC100_UFCON_DEFAULT, + .ucon = SMDKC100_UCON_DEFAULT, + .ulcon = SMDKC100_ULCON_DEFAULT, + .ufcon = SMDKC100_UFCON_DEFAULT, }, [2] = { .hwport = 2, .flags = 0, - .ucon = S5PC100_UCON_DEFAULT, - .ulcon = S5PC100_ULCON_DEFAULT, - .ufcon = S5PC100_UFCON_DEFAULT, + .ucon = SMDKC100_UCON_DEFAULT, + .ulcon = SMDKC100_ULCON_DEFAULT, + .ufcon = SMDKC100_UFCON_DEFAULT, }, [3] = { .hwport = 3, .flags = 0, - .ucon = S5PC100_UCON_DEFAULT, - .ulcon = S5PC100_ULCON_DEFAULT, - .ufcon = S5PC100_UFCON_DEFAULT, + .ucon = SMDKC100_UCON_DEFAULT, + .ulcon = SMDKC100_ULCON_DEFAULT, + .ufcon = SMDKC100_UFCON_DEFAULT, }, }; @@ -128,7 +134,6 @@ static struct platform_device smdkc100_lcd_powerdev = { static struct s3c_fb_pd_win smdkc100_fb_win0 = { /* this is to ensure we use win0 */ .win_mode = { - .pixclock = 1000000000000ULL / ((8+13+3+800)*(7+5+1+480)*80), .left_margin = 8, .right_margin = 13, .upper_margin = 7, @@ -137,6 +142,7 @@ static struct s3c_fb_pd_win smdkc100_fb_win0 = { .vsync_len = 1, .xres = 800, .yres = 480, + .refresh = 80, }, .max_bpp = 32, .default_bpp = 16, @@ -149,16 +155,55 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = { .setup_gpio = s5pc100_fb_gpio_setup_24bpp, }; +static struct s3c_ide_platdata smdkc100_ide_pdata __initdata = { + .setup_gpio = s5pc100_ide_setup_gpio, +}; + +static uint32_t smdkc100_keymap[] __initdata = { + /* KEY(row, col, keycode) */ + KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), + KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), + KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), + KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) +}; + +static struct matrix_keymap_data smdkc100_keymap_data __initdata = { + .keymap = smdkc100_keymap, + .keymap_size = ARRAY_SIZE(smdkc100_keymap), +}; + +static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = { + .keymap_data = &smdkc100_keymap_data, + .rows = 2, + .cols = 8, +}; + static struct platform_device *smdkc100_devices[] __initdata = { + &s3c_device_adc, + &s3c_device_cfcon, &s3c_device_i2c0, &s3c_device_i2c1, &s3c_device_fb, &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_hsmmc2, + &s3c_device_ts, + &s3c_device_wdt, &smdkc100_lcd_powerdev, &s5pc100_device_iis0, + &samsung_device_keypad, &s5pc100_device_ac97, + &s3c_device_rtc, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s5pc100_device_spdif, +}; + +static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { + .delay = 10000, + .presc = 49, + .oversampling_shift = 2, }; static void __init smdkc100_map_io(void) @@ -170,6 +215,8 @@ static void __init smdkc100_map_io(void) static void __init smdkc100_machine_init(void) { + s3c24xx_ts_set_platdata(&s3c_ts_platform); + /* I2C */ s3c_i2c0_set_platdata(NULL); s3c_i2c1_set_platdata(NULL); @@ -177,6 +224,11 @@ static void __init smdkc100_machine_init(void) i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); s3c_fb_set_platdata(&smdkc100_lcd_pdata); + s3c_ide_set_platdata(&smdkc100_ide_pdata); + + samsung_keypad_set_platdata(&smdkc100_keypad_data); + + s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD); /* LCD init */ gpio_request(S5PC100_GPD(0), "GPD"); @@ -187,8 +239,6 @@ static void __init smdkc100_machine_init(void) MACHINE_START(SMDKC100, "SMDKC100") /* Maintainer: Byungho Min <bhmin@samsung.com> */ - .phys_io = S3C_PA_UART & 0xfff00000, - .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, .boot_params = S5P_PA_SDRAM + 0x100, .init_irq = s5pc100_init_irq, .map_io = smdkc100_map_io, diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c index 6eba6cb8e2f..d31c0f3fe22 100644 --- a/arch/arm/mach-s5pc100/setup-fb-24bpp.c +++ b/arch/arm/mach-s5pc100/setup-fb-24bpp.c @@ -22,27 +22,15 @@ #define DISR_OFFSET 0x7008 -void s5pc100_fb_gpio_setup_24bpp(void) +static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr) { - unsigned int gpio = 0; - - for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } - - for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } - - for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2)); +} - for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } +void s5pc100_fb_gpio_setup_24bpp(void) +{ + s5pc100_fb_setgpios(S5PC100_GPF0(0), 8); + s5pc100_fb_setgpios(S5PC100_GPF1(0), 8); + s5pc100_fb_setgpios(S5PC100_GPF2(0), 8); + s5pc100_fb_setgpios(S5PC100_GPF3(0), 4); } diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c index dd3174e6ecc..eaef7a3bda4 100644 --- a/arch/arm/mach-s5pc100/setup-i2c0.c +++ b/arch/arm/mach-s5pc100/setup-i2c0.c @@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */ void s3c_i2c0_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PC100_GPD(3), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c index d1fec26b69e..aaff74a90de 100644 --- a/arch/arm/mach-s5pc100/setup-i2c1.c +++ b/arch/arm/mach-s5pc100/setup-i2c1.c @@ -23,8 +23,6 @@ struct platform_device; /* don't need the contents */ void s3c_i2c1_cfg_gpio(struct platform_device *dev) { - s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgall_range(S5PC100_GPD(5), 2, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); } diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c new file mode 100644 index 00000000000..223aae04446 --- /dev/null +++ b/arch/arm/mach-s5pc100/setup-ide.c @@ -0,0 +1,57 @@ +/* linux/arch/arm/mach-s5pc100/setup-ide.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5PC100 setup information for IDE + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/gpio.h> +#include <linux/io.h> + +#include <mach/regs-clock.h> +#include <plat/gpio-cfg.h> + +static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr) +{ + s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4)); + + for (; nr > 0; nr--, base++) + s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4); +} + +void s5pc100_ide_setup_gpio(void) +{ + u32 reg; + + /* Independent CF interface, CF chip select configuration */ + reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f); + writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG); + + /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */ + s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8); + + /*CF_Data[0 - 7] */ + s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8); + + /* CF_Data[8 - 15] */ + s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8); + + /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */ + s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4); + + /* EBI_OE, EBI_WE */ + s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0)); + + /* CF_OE, CF_WE */ + s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2)); + + /* CF_CD */ + s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2)); + s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE); +} diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c new file mode 100644 index 00000000000..ada377f0c20 --- /dev/null +++ b/arch/arm/mach-s5pc100/setup-keypad.c @@ -0,0 +1,23 @@ +/* linux/arch/arm/mach-s5pc100/setup-keypad.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * GPIO configuration for S5PC100 KeyPad device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/gpio.h> +#include <plat/gpio-cfg.h> + +void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) +{ + /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */ + s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3)); + + /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */ + s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3)); +} diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c index 7769c760c9e..03c02d04c68 100644 --- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c @@ -20,11 +20,11 @@ #include <plat/gpio-cfg.h> #include <plat/regs-sdhci.h> +#include <plat/sdhci.h> void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) { - unsigned int gpio; - unsigned int end; + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; unsigned int num; num = width; @@ -32,55 +32,40 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) if (width == 8) num = width - 2; - end = S5PC100_GPG0(2 + num); - /* Set all the necessary GPG0/GPG1 pins to special-function 0 */ - for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2)); - if (width == 8) { - for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } - } + if (width == 8) + s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2)); + } } void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) { - unsigned int gpio; - unsigned int end; - - end = S5PC100_GPG2(2 + width); + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; /* Set all the necessary GPG2 pins to special-function 2 */ - for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2)); + } } void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) { - unsigned int gpio; - unsigned int end; - - end = S5PC100_GPG3(2 + width); + struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; /* Set all the necessary GPG3 pins to special-function 2 */ - for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) { - s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } + s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2)); - s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP); - s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2)); + if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { + s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP); + s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2)); + } } diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c index ea7ff19adb9..f16946e456e 100644 --- a/arch/arm/mach-s5pc100/setup-sdhci.c +++ b/arch/arm/mach-s5pc100/setup-sdhci.c @@ -26,10 +26,10 @@ /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ char *s5pc100_hsmmc_clksrcs[4] = { - [0] = "hsmmc", - [1] = "hsmmc", - /* [2] = "mmc_bus", not yet successfully used yet */ - /* [3] = "48m", - note not successfully used yet */ + [0] = "hsmmc", /* HCLK */ + /* [1] = "hsmmc", - duplicate HCLK entry */ + [2] = "sclk_mmc", /* mmc_bus */ + /* [3] = "48m", - note not successfully used yet */ }; |